Fractional clock generator with ramp control including fixed time interval and coarse/fine frequency change steps

Patent metadata

Field	Value
Publication number	US-10014869-B1
Application number	US-201715453712-A
Country	US
Kind code	B1
Filing date	Mar 8, 2017
Priority date	Mar 8, 2017
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a frequency of an input clock signal. The frequency ramp control circuit is configured to provide the fractional clock divider a set of divider ratios so that the frequency of the output clock signal is ramped in steps from a current frequency to a target frequency. The frequency ramp control circuit is configured to produce frequency change steps each having substantially the same duration. The frequency ramp control circuit is also configured to provide the set of divider ratios such as a first portion of the frequency ramp is performed using coarse frequency changes and a second portion of the ramp is performed using at least one fine frequency change.

First claim

What is claimed is:

1. An apparatus, comprising:
a fractional clock divider, comprising:
a first counter configured to generate an index of edge positions of an input clock signal; and
an output clock generator configured to generate an output clock signal based on a current divider ratio and the index;

a frequency ramp control circuit, comprising:
a second counter configured to generate a first signal based on a selected duration for a frequency change step of the output clock signal, wherein the second counter is synchronized with the first counter, wherein the first counter is configured to generate a second signal indicating an end of a sequence of edges of the output clock signal, wherein the second counter is primed based on the second signal; and
a divider ratio determining device configured to determine the current divider ratio; and

a logic circuit configured to generate a fourth signal indicating an end of the frequency change step based on the first and second signals, wherein the first counter is primed based on the fourth signal.

2. The apparatus of claim 1 , wherein the second counter comprises:
a base counter configured to generate a count based on a modulo set by the current divider ratio; and
a loop counter configured to generate the first signal based on the count and a signal for setting the selected duration for the frequency change step.

3. The apparatus of claim 1 , wherein the divider ratio determining device is configured to generate a set of divider ratios including the current divider ratio to ramp a current frequency of the output clock signal to a target frequency.

4. The apparatus of claim 3 , wherein the divider ratio determining device is configured to:
select a first set of same denominators for a first subset of the set of divider ratios; and
select a second set of one or more same denominators for a second subset of the set of divider ratios.

5. The apparatus of claim 4 , wherein each of the same denominators of the first set is less than each of the one or more same denominators of the second set.

6. The apparatus of claim 4 , wherein the first set of same denominators are used to achieve a majority of the ramp of the current frequency to the target frequency.

7. The apparatus of claim 4 , wherein the first set of same denominators are used to achieve at least a defined percentage of the ramp of the current frequency to the target frequency.

8. The apparatus of claim 4 , wherein the divider ratio determining device is configured to select a set of sequential numerators for the first subset of divider ratios.

Assignees

• Qualcomm Inc

Inventors

• Bowles Kevin
• Pal Dipti Ranjan

Classifications

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K2005/00013

  Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse · CPC title

• H03L7/1974 Primary

  for fractional frequency division · CPC title

• H03K21/10 Primary

  comprising logic circuits · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title