Solar cell and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10014419-B2
Application number	US-201715643180-A
Country	US
Kind code	B2
Filing date	Jul 6, 2017
Priority date	Nov 28, 2014
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A method for manufacturing a solar cell can include a tunnel layer forming step of forming a tunnel layer on a first surface of a semiconductor substrate, a first conductive type semiconductor region forming step of forming a first conductive type semiconductor region on the first surface of the semiconductor substrate, a second conductive type semiconductor region forming step of forming a second conductive type semiconductor region by doping impurities of a second conductive type into a second surface of the semiconductor substrate, a first passivation film forming step of forming a first passivation film on the first conductive type semiconductor region and an electrode forming step of forming a first electrode connected to the first conductive type semiconductor region and a second electrode connected to the second conductive type semiconductor region.

First claim

What is claimed is:

1. A method for manufacturing a solar cell, comprising:
a tunnel layer forming step of forming a tunnel layer on a first surface of a semiconductor substrate, a second surface of the semiconductor substrate and a side of the semiconductor substrate;
a first conductive type semiconductor region forming step of forming a first conductive type semiconductor region on the first surface of the semiconductor substrate and the second surface of the semiconductor substrate;
a second conductive type semiconductor region forming step of forming a second conductive type semiconductor region by doping impurities of the second conductive type into the second surface of the semiconductor substrate;
a removing step of removing the tunnel layer and the first conductive type semiconductor region placed at least on the second surface of the semiconductor substrate prior to the second conductive type semiconductor region forming step after the first conductive type semiconductor region forming step;
a first passivation film forming step of forming a first passivation film on the first conductive type semiconductor region; and
an electrode forming step of forming a first electrode connected to the first conductive type semiconductor region and a second electrode connected to the second conductive type semiconductor region,
wherein the removing step further comprises forming an isolation portion by removing the tunnel layer on the side of the semiconductor substrate and an edge portion of the first conductive type semiconductor region, and
wherein the first passivation film covers the first surface of the semiconductor substrate along with the isolation portion.

2. The method of claim 1 , further comprising a step of forming an opening portion in the first passivation film after the first passivation film forming step.

3. The method of claim 2 , wherein the step of forming the opening portion in the first passivation film is performed by thermal treatment in the electrode forming step.

4. The method of claim 3 , wherein the electrode forming step comprises a first electrode forming step of forming the first electrode, and
wherein the first electrode forming step comprises printing a paste for forming first finger electrodes and a paste for forming a first bus bar on the first passivation film and performing thermal treatment on the pastes.

5. The method of claim 4 , wherein in the first electrode forming step, a highest temperature for the thermal treatment is between 795° C. to 870° C.

6. The method of claim 4 , wherein in the first electrode forming step, the paste for the first finger electrodes and the paste for the first bus bar are printed through a single process.

7. The method of claim 6 , wherein a material in the paste for the first finger electrodes is identical to a material in the paste for the first bus bar.

8. The method of claim 4 , wherein in the first electrode forming step, the paste for the first finger electrodes and the paste for the first bus bar are printed using separate printing processes.

9. The method of claim 8 , wherein a material in the paste for the first finger electrodes and a material in the paste for the first bus bar are different.

10. The method of claim 1 , further comprising an intrinsic semiconductor layer forming step of forming an intrinsic semiconductor layer on the tunnel layer formed on the first surface of the semiconductor substrate between the tunnel layer forming step and the first conductive type semiconductor region forming step, and,
in the first conductive type semiconductor region forming step, impurities of the first conductive type is doped into the intrinsic semiconductor layer formed on the first surface of the semiconductor substrate.

11. The method of claim 1 , wherein the first surface of the semiconductor substrate is the back surface of the semiconductor substrate.

12. The method of claim 1 , the first conductive type semiconductor region is formed by a thermal expansion of impurities of a first conductive type.

13. The method of claim 1 , wherein the removing step further comprises:
forming a mask layer having a smaller area than the semiconductor substrate on the first conductive type semiconductor region on the first surface of the semiconductor substrate;
etching the first conductive type semiconductor region and the tunnel layer in a portion in which the mask layer is not formed; and
removing the mask layer.

14. The method of claim 1 , further comprising forming an additional passivation film covering the second conductive type semiconductor region between the step of forming the second conductive type semiconductor region and the step of forming the first passivation film.

15. The method of claim 14 , wherein the additional passivation film is formed on the side of the semiconductor substrate, and the first passivation film is formed on the additional passivation film.

16. The method of claim 1 , wherein the first electrode is a front electrode positioned on the second surface of the semiconductor substrate, and the second electrode is a back electrode positioned on the first surface of the semiconductor substrate.

Assignees

• Lg Electronics Inc

Inventors

• Ha Jungmin
• Kim Sungjin
• Cheong Juhwa
• Ahn Junyong
• Choi Hyungwook
• Chang Wonjae
• Kim Jaesung

Classifications

• Y02E10/50

  Photovoltaic [PV] energy · CPC title

• H10F71/133

  Providing edge isolation · CPC title

• H10F10/14

  Photovoltaic cells having only PN homojunction potential barriers · CPC title

• H10F10/165

  the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells · CPC title

• H01L31/1824

  Electricity · mapped topic