Semiconductor device with passivation layer for control of leakage current

Patent metadata

Field	Value
Publication number	US-10014401-B2
Application number	US-201715414156-A
Country	US
Kind code	B2
Filing date	Jan 24, 2017
Priority date	Jan 25, 2016
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A semiconductor device includes a semiconductor structure including a substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer, a first passivation pattern provided on the semiconductor structure, and first and second conductive patterns provided on the semiconductor structure and spaced from the first passivation pattern.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor structure comprising a substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer;
a first conductive pattern on the semiconductor structure;
a second conductive pattern spaced apart from the first conductive pattern in a first direction parallel to a top surface of the substrate;
a first passivation pattern provided between the first and second conductive patterns; and
a second passivation pattern provided on the first passivation pattern,
wherein the first conductive pattern, the first passivation pattern, and the second conductive pattern are arranged in the first direction,
wherein the first passivation pattern is directly in contact with a top surface of the semiconductor structure, and
wherein each of the first and second conductive patterns is spaced apart from the first passivation pattern in the first direction, and
the first and second passivation patterns are spaced apart from each other.

2. The semiconductor device of claim 1 ,
wherein a first air gap is provided between the first and second passivation patterns, and
wherein the first and second passivation patterns are spaced apart from each other by the first air gap.

3. The semiconductor device of claim 2 , wherein the first and second passivation patterns are exposed by the first air gap and the first and second passivation patterns exposed by the first air gap are spaced from each other.

4. The semiconductor device of claim 2 , wherein the second passivation pattern covers a side of the first conductive pattern and a side of the second conductive pattern, which face each other.

5. The semiconductor device of claim 2 , wherein the second passivation pattern covers an upper surface of the semiconductor structure immediately adjacent to each of a side of the first conductive pattern and a side of the second conductive pattern, which face each other.

6. The semiconductor device of claim 2 , wherein at least a part of an upper surface of the semiconductor structure between the first and second conductive patterns is exposed by the first air gap.

7. The semiconductor device of claim 2 , further comprising a gap fill pattern penetrating the second passivation pattern to contact the semiconductor structure.

8. The semiconductor device of claim 7 , wherein a lower part of the gap fill pattern is exposed by the first air gap.

9. The semiconductor device of claim 7 , wherein a lower part of the gap fill pattern contacts an end part of the first passivation pattern between the first and second conductive patterns.

10. The semiconductor device of claim 7 , wherein the gap fill pattern is spaced from an area between the first and second conductive patterns along an extension direction of the first and second conductive patterns.

11. The semiconductor device of claim 2 , further comprising a third conductive pattern spaced from the first conductive pattern with the second conductive pattern therebetween,
wherein the third conductive pattern is spaced from the first passivation pattern;
the second passivation pattern is spaced from the first passivation pattern between the second and third conductive patterns and a second air gap is provided between the first passivation pattern and the second passivation pattern, between the second and third conductive patterns; and
the first and third conductive patterns are electrically connected to each other.

12. The semiconductor device of claim 2 , further comprising:
a gate insulating pattern interposed between the second conductive pattern and the semiconductor structure; and
a third conductive pattern disposed on an opposite side of the first conductive pattern on the basis of the second conductive pattern,
wherein the third conductive pattern is spaced from the first passivation pattern; and
the second passivation pattern is spaced from the first passivation pattern between the second and third conductive patterns and a second air gap is provided between the first passivation pattern and the second passivation pattern, between the second and third conductive patterns.

13. The semiconductor device of claim 1 , wherein the first conductive pattern comprises a metal that ohmic-contacts the semiconductor structure; and
the second conductive pattern comprises a metal that is schottky-junctioned to the semiconductor structure.

14. The semiconductor device of claim 1 , wherein the first semiconductor layer comprises a 2-dimensional (2-DEG) electron gas layer in an area adjacent to a boundary of the first and second semiconductor layers.

15. The semiconductor device of claim 14 , wherein the first semiconductor layer comprises a GaN layer and the second semiconductor layer comprises an AlGaN layer.

16. The semiconductor device of claim 1 , wherein the semiconductor structure further comprises a capping layer on the second semiconductor layer.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• NA Jeho
• Lee Hyung Seok
• Jun Chi Hoon
• Ko Sang Choon
• Kwack Myungjoon
• Park Young Rak
• Chang Woojin
• JANG Hyun-Gyu
• Jung Dong Yun

Classifications

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/137 Primary

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/134

  the encapsulations being in grooves in the semiconductor body · CPC title

• H10W74/124

  the encapsulations having cavities other than that occupied by chips · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title