Array substrate with thin film transistor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10014329-B2
Application number	US-201414436843-A
Country	US
Kind code	B2
Filing date	Sep 11, 2014
Priority date	Mar 31, 2014
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

An array substrate and manufacturing method thereof and display device are provided. The method of manufacturing the array substrate includes forming a pattern including a gate electrode, a gate line, a common electrode line and a gate insulating layer on a substrate; forming a pattern including a data line, a source electrode, a drain electrode and an active layer; forming a pattern including an insulating interlayer over the pattern of the source electrode, the drain electrode and the active layer; forming a pattern including a first transparent electrode over the insulating interlayer; forming a pattern including a passivation layer over the first transparent electrode; and forming a pattern including a second transparent electrode over the passivation layer. The method can efficiently prevent the ITO process polluting the TFT channel.

First claim

What is claimed is:

1. A method of manufacturing an array substrate, comprising:
forming a pattern including a gate electrode, a gate line, a common electrode line and a gate insulating layer on a substrate;
forming a pattern including a data line, a source electrode, a drain electrode and an active layer;
forming a pattern including an insulating interlayer over the pattern of the source electrode, the drain electrode and the active layer;
forming a pattern including a first transparent electrode, and a first via hole through at least the insulating interlayer to allow the first transparent electrode to be connected with the common electrode line;
forming a pattern including a passivation layer over the first transparent electrode; and
then, forming a pattern including a second transparent electrode, and a second via hole through the passivation layer to allow the second transparent electrode to be connected with the drain electrode.

2. The method of manufacturing the array substrate according to claim 1 , further comprising:
applying photoresist on the insulating interlayer;
exposing and developing the photoresist by using a double-tone mask to remove a portion of the photoresist corresponding to a region where the pattern of the common electrode line is located, partially remain a portion of the photoresist corresponding to a region where the pattern of the first transparent electrode is located, and fully remain portions of the photoresist of other regions;
etching exposed insulating interlayer to form the first via hole so as to expose the common electrode line;
processing the photoresist by an ash process to remove a portion of the photoresist corresponding to the region where the pattern of the first transparent electrode is located, and remain portions of the photoresist outside of the regions where the first transparent electrode and the first via hole are located; and
forming a first transparent conducting thin film and removing the remained portions of the photoresist and the first transparent conducting thin film thereon to form the first transparent electrode.

3. The method of manufacturing the array substrate according to claim 2 , further comprising:
forming the second via hole in a region, corresponding to the drain electrode, of the passivation layer.

4. The method of manufacturing the array substrate according to claim 1 , further comprising:
performing a hydrogen plasma process to a channel region formed between the source electrode and the drain electrode before forming the pattern including the insulating interlayer over the pattern of the source electrode, the drain electrode and the active layer.

5. The method of manufacturing the array substrate according to claim 2 , further comprising: performing a hydrogen plasma process to a channel region formed between the source electrode and the drain electrode before forming the pattern including the insulating interlayer over the pattern of the source electrode, the drain electrode and the active layer.

6. The method of manufacturing the array substrate according to claim 1 , wherein the insulating interlayer has a thickness of 50 Å-500 Å.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Bai Jinchao
• Ding Xiangqian
• Liu Yao
• Li Liangliang
• Guo Zongjie

Classifications

• H01L27/1288

  Electricity · mapped topic

• H01L27/1248 Primary

  Electricity · mapped topic

• H01L27/127

  Electricity · mapped topic

• H01L27/124

  Electricity · mapped topic

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title