Thin film transistor array substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-10014327-B2
Application number	US-201715585171-A
Country	US
Kind code	B2
Filing date	May 3, 2017
Priority date	Jun 5, 2014
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A thin film transistor array substrate for a display device generally includes: a substrate; a plurality of gate lines and a plurality of data lines arranged on the substrate intersecting with and insulated from each other; and a plurality of pixel elements arranged in areas defined by the gate lines and the data lines. At least one of the pixel elements includes: a switch element; an insulation layer located on the switch element; and a pixel electrode located at the insulation layer. The insulation layers of the pixel elements define a plurality of vias. The pixel electrodes of two adjacent pixel elements are electrically coupled with the corresponding switch elements of the two adjacent pixel elements through a common via defined by the insulation layers of the two adjacent pixel elements. The two adjacent pixel elements are disposed along extensions of the plurality of the gate lines.

First claim

The invention claimed is:

1. A thin film transistor array substrate for a display device, the array substrate comprising:
a substrate;
a plurality of gate lines disposed on the substrate;
a plurality of data lines disposed on the substrate, wherein the plurality of the gate lines and the plurality of the data lines intersect with each other to define a plurality of areas and are insulated from each other; and
a plurality of pixel elements disposed in the plurality of areas defined by the plurality of the gate lines and the plurality of the data lines, wherein a first part of the pixel elements are first pixel elements, and a second part of the pixel elements are second pixel elements, wherein one second pixel element is structured centrally symmetric with respect to one first pixel element, and one first pixel element is rotated about a center point left or right by 180° into the one second pixel element, and the first pixel elements and the second pixel elements are disposed alternately along extensions of the plurality of the data lines;
wherein two gate lines are disposed between two adjacent first pixel element and second pixel element along the extensions of the plurality of the data lines, and spacer are disposed between the two gate lines.

2. The array substrate of claim 1 , wherein:
the plurality of the pixel elements each comprise a switch element;
the plurality of the pixel elements define a plurality of rows of pixels elements arranged along extensions of the plurality of the gate lines and a plurality of columns of pixel elements arranged along the extensions of the plurality of the data lines;
one of two adjacent rows of the plurality of rows of pixel elements comprises only the first pixel elements, and the other of the two adjacent rows comprises only the second pixel elements.

3. The array substrate of claim 2 , wherein the switch elements of the M-th row of the first pixel elements are coupled with the M-th level of the plurality of the gate lines, and the switch elements of the (M+1)-th row of the second pixel elements are coupled with the (M+1)-th level of the plurality of the gate lines, M is a natural number.

4. The array substrate of claim 3 , wherein:
in the N-th column, the switch elements of the first pixel elements are coupled with the N-th column of the plurality of the data lines, and the switch elements of the second pixel elements are coupled with the (N+1)-th column of the plurality of the data lines, N is a natural number.

5. The array substrate of claim 1 , wherein the first pixel elements and the second pixel elements are arranged alternately along extensions of the plurality of the gate lines.

6. The array substrate of claim 5 , wherein
the plurality of the pixel elements each comprise a switch element;
the plurality of the pixel elements define a plurality of rows of pixels elements arranged along extensions of the plurality of the gate lines and a plurality of columns of pixel elements arranged along the extensions of the plurality of the data lines;
the (2M+1)-th level of the plurality of the gate lines are coupled with the switch elements of the (2M+1)-th row of the first pixel elements and the switch elements of the (2M+2)-th row of the first pixel elements, M is a natural number;
the (2M+2)-th level of the plurality of the gate lines are coupled with the switch elements of the (2M+2)-th row of the second pixel elements and the switch elements of the (2M+3)-th row of the second pixel elements.

7. The array substrate of claim 6 , wherein:
in the N-th column, the switch elements of the first pixel elements and the switch elements of the second pixel elements are coupled respectively with the N-th column of the plurality of the data lines.

8. The array substrate of claim 6 , wherein:
among the first pixel elements and the second pixel elements adjacent along the extensions of the plurality of the data lines, the switch elements of the first pixel elements are coupled with the N-th column of the plurality of the data lines, and the switch elements of the second pixel elements are coupled with the (N+1)-th column of the plurality of the data lines.

9. The array substrate of claim 1 , wherein groups of the first pixel elements comprising more than one of the first pixel element and groups of the second pixel elements comprising more than one of the second pixel element are arranged alternately along extensions of the plurality of the gate lines.

10. The array substrate of claim 9 , wherein each group of the first pixel elements and each group of the second pixel elements include an equal number of the first or second pixel elements.

11. The array substrate of claim 9 , wherein,
the plurality of the pixel elements each include a switch element;
the plurality of the pixel elements define a plurality of rows of pixels elements arranged along extensions of the plurality of the gate lines and a plurality of columns of pixel elements arranged along the extensions of the plurality of the data lines;
the (2M+1)-th level of the plurality of the gate lines are coupled with the switch elements of the (2M+1)-th row of the first pixel elements and the switch elements of the (2M+2)-th row of the first pixel elements, and the (2M+2)-th level of the plurality of the gate lines are coupled with the switch elements of the (2M+2)-th row of the second pixel elements and the switch elements of the (2M+3)-th row of the second pixel elements, and wherein M is a natural number.

12. The array substrate of claim 11 , wherein:
in the N-th column, the switch elements of the first pixel elements are coupled respectively with the N-th column of the plurality of the data lines and the switch elements of the second pixel elements are coupled respectively with the (N+1)-th column of the plurality of the data lines.

Assignees

• Xiamen Tianma Micro Electronics Co Ltd
• Tianma Micro Electronics Co Ltd

Inventors

• Li Weiping

Classifications

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F2001/13685

  Physics · mapped topic

• H01L27/124 Primary

  Electricity · mapped topic