Package assembly for embedded die and associated techniques and configurations

Patent metadata

Field	Value
Publication number	US-10014263-B2
Application number	US-201715611428-A
Country	US
Kind code	B2
Filing date	Jun 1, 2017
Priority date	Jun 26, 2013
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations. In one embodiment, an apparatus includes a package assembly comprising a die attach layer, a die coupled with the die attach layer, the die having an active side including active devices of the die and an inactive side disposed opposite to the active side, a reinforced plate coupled with the die attach layer, the reinforced plate having a first side and a second side disposed opposite to the first side and a cavity disposed in the reinforced plate and one or more build-up layers coupled with the second side of the reinforced plate, the one or more build-up layers including an insulator and conductive features disposed in the insulator, the conductive features being electrically coupled with the die, wherein the inactive side of the die is in direct contact with the die attach layer, the first side of the reinforced plate is in direct contact with the die attach layer and the die is disposed in the cavity. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A package assembly comprising:
a die attach layer having a first side and a second side, wherein the die attach layer is an electrically insulative material, wherein the second side of the die attach layer is exposed to couple with an electrical component by one or more package-level interconnects;
a die coupled with the die attach layer, the die having an active side including active devices of the die and an inactive side disposed opposite to the active side, the inactive side of the die coupled to the first side of the die attach layer, wherein the die attach layer is used as a substrate for attachment of the die and the die is in direct contact with the die attach layer;
a reinforced plate coupled with the die attach layer, the reinforced plate having an electrically conductive core, a first side and a second side disposed opposite to the first side and a cavity disposed in the reinforced plate, the first side of the reinforced plate coupled with the first side of the die attach layer and the die is disposed in the cavity; and
one or more build-up layers coupled with the second side of the reinforced plate, the one or more build-up layers including an insulator and conductive features disposed in the insulator, the conductive features being electrically coupled with the die without wire bonds, wherein the die attach layer has openings to expose interconnects of the first side of the reinforced plate to couple with the one or more package-level interconnects through the openings of the die attach layer.

2. The package assembly of claim 1 , wherein the electrically conductive core is a metal core.

3. The package assembly of claim 2 , wherein the metal core is copper or aluminum.

4. The package assembly of claim 2 , wherein the reinforced plate includes interconnects to electrically couple the first side and the second side of the reinforced plate.

5. The package assembly of claim 4 , wherein the reinforced plate includes an electrically insulative layer disposed on the electrically conductive core to provide a barrier between the electrically conductive core and the interconnects that electrically couple the first side and the second side of the reinforced plate.

6. The package assembly of claim 1 , wherein the one or more build-up layers cover all of the second side of the reinforced plate.

7. The package assembly of claim 1 , wherein the die is a first die, the package assembly further comprising a second die electrically coupled with the first die.

8. The package assembly of claim 7 , wherein:
the second die is electrically coupled with the first die through electrical routing features of the one or more build-up layers; and
the reinforced plate includes plated through holes (PTHs) coupled with the interconnects of the first side of the reinforced plate to route electrical signals of the first die and the second die to the one or more package-level interconnects.

9. The package assembly of claim 1 , wherein the die is an integrated circuit die and the inactive side of the die is not electrically coupled with the one or more package-level interconnects.

10. The package assembly of claim 1 , wherein the second side of the die attach layer is free of coupling with any additional layers.

11. The package assembly of claim 1 , further comprising:
a die encapsulant material disposed in the cavity and at least partially encapsulating the active side of the die, wherein the die is electrically coupled with electrical routing features of the one or more build-up layers through via structures that extend through the die encapsulant material.

12. The package assembly of claim 1 , wherein the die attach layer is a non-composite layer.

13. A computing device comprising:
a circuit board; and
a package assembly coupled with the circuit board, the package assembly comprising:
a die attach layer having a first side and a second side, wherein the die attach layer is an electrically insulative material;
a die coupled with the die attach layer, the die having an active side including active devices of the die and an inactive side disposed opposite to the active side, the inactive side of the die coupled to the first side of the die attach layer, wherein the die attach layer is used as a substrate for attachment of the die;
a reinforced plate coupled with the die attach layer, the reinforced plate having an electrically conductive core, a first side and a second side disposed opposite to the first side and a cavity disposed in the reinforced plate, the first side of the reinforced plate coupled with the first side of the die attach layer and the die is disposed in the cavity; and
one or more build-up layers coupled with the second side of the reinforced plate, the one or more build-up layers including an insulator and conductive features disposed in the insulator, the conductive features being electrically coupled with the die without wire bonds, wherein the die attach layer has openings to expose interconnects of the first side of the reinforced plate, wherein the second side of the die attach layer is coupled with the circuit board by one or more package-level interconnects coupled to the interconnects of the first side of the reinforced plate through the openings of the die attach layer.

14. The computing device of claim 13 , wherein the reinforced electrically conductive core is a metal core.

15. The computing device of claim 14 , wherein the metal core is copper or aluminum.

16. The computing device of claim 13 , wherein the reinforced plate includes interconnects to electrically couple the first side and the second side of the reinforced plate.

17. The computing device of claim 16 , wherein the reinforced plate includes an electrically insulative layer disposed on the electrically conductive core to provide a barrier between the electrically conductive core and the interconnects that electrically couple the first side and the second side of the reinforced plate.

18. The computing device of claim 13 , wherein the die is in direct contact with the die attach layer.

19. The computing device of claim 18 , wherein the one or more build-up layers cover all of the second side of the reinforced plate.

20. The computing device of claim 13 , wherein the computing device is a mobile computing device further comprising:
one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board.

Assignees

• Intel Corp

Inventors

• Shuto Takashi

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title