Semiconductor device

Patent metadata

Field	Value
Publication number	US-10014254-B2
Application number	US-201715647946-A
Country	US
Kind code	B2
Filing date	Jul 12, 2017
Priority date	Mar 26, 2015
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a first impurity region in a first region of a semiconductor substrate;
forming a second impurity region in a second region of the semiconductor substrate;
forming a first channel region by an epitaxial growth above the first impurity region;
forming an isolation film that separates the first region and the second region in the semiconductor substrate;
forming a first gate insulating film above the first region;
forming a second gate insulating film above the second region;
forming a gate electrode film above the first gate insulating film and the second gate insulating film;
forming a first gate electrode of the gate electrode film above the first region remaining the gate electrode film above the second region;
forming a first sidewall insulating film on a sidewall of the first gate electrode and above the first region;
forming a second gate electrode of the gate electrode film above the second region;
forming a second sidewall insulating film on a sidewall of the second gate electrode and above the second region;
forming a first source region and a first drain region on both sides of the first gate electrode above the first region; and
forming a second source region and a second drain region on both sides of the second gate electrode above the second region,
wherein:
a first transistor including the first impurity region, the first channel region, the first gate insulating film, the first gate electrode, the first sidewall insulating film, the first source region and the first drain region;
a second transistor including the second impurity region, the second gate insulating film, the second gate electrode, the second sidewall insulating film, the second source region and the second drain region;
the first transistor storing information by accumulating charge in the first sidewall insulating film;
a width of the first sidewall insulating film is larger than a width of the second sidewall insulating film; and
a thickness of the first gate insulating film is larger than a thickness of the second gate insulating film.

2. The method according to claim 1 , further comprising forming a second channel region by the epitaxial growth above the second impurity region, wherein the second transistor further including the second channel region.

3. The method according to claim 2 , wherein an impurity concentration of the second impurity region is higher than an impurity concentration of the second channel region.

4. The method according to claim 3 , further comprising forming a fourth impurity region below the second impurity region of the semiconductor substrate, wherein an impurity concentration of the fourth impurity region is higher than an impurity concentration of the second channel region.

5. The method according to claim 1 , wherein the first sidewall insulating film includes a stacked structure of an oxide film and a nitride film.

6. The method according to claim 1 , wherein an impurity concentration of the first impurity region is higher than an impurity concentration of the first channel region.

7. The method according to claim 6 , further comprising forming a third impurity region below the first impurity region of the semiconductor substrate, wherein an impurity concentration of the third impurity region is higher than an impurity concentration of the first channel region.

8. The method according to claim 1 , further comprising:
forming a ground line above the semiconductor substrate, the ground line which extends in a first direction in planar view and is connected to one of the first source region and the first drain region; and
forming a bit line above the semiconductor substrate, the bit line which extends in a second direction different from the first direction in the planar view and is connected to the other one of the first source region and the first drain region; wherein,
the forming of the first gate electrode includes forming the first gate electrode as a word line which extends in the first direction in the planar view.

9. The method according to claim 1 , wherein:
the first source region and the first drain region contain a first impurity of a first conductivity type; and
the first impurity region contains a second impurity of a second conductivity type different from the first conductivity type.

10. The method according to claim 1 , further comprising:
forming a fifth impurity region in a third region of the semiconductor substrate;
forming a third gate insulating film above the third region;
forming a third gate electrode above the third gate insulating film;
forming a third sidewall insulating film on a sidewall of the third gate electrode and above the third region; and
forming a third source region and a third drain region on both sides of the third gate electrode in the third region; wherein:
a width of the first sidewall insulating film is larger than a width of the third sidewall insulating film; and
a thickness of the first gate insulating film and a thickness of the third gate insulating film are larger than a thickness of the second gate insulating film.

11. A method for manufacturing a semiconductor device, comprising:
forming a first impurity region in a first region of a semiconductor substrate;
forming a second impurity region in a second region of the semiconductor substrate;
forming a first channel region by an epitaxial growth above the first impurity region;
forming an isolation film that separates the first region and the second region in the semiconductor substrate;
forming a first gate insulating film above the first region;
forming a second gate insulating film above the second region;
forming a gate electrode film above the first gate insulating film and the second gate insulating film;
forming a first gate electrode of the gate electrode film above the first region remaining the gate electrode film above the second region;
forming a first sidewall insulating film on a sidewall of the first gate electrode and above the first region;
forming a second gate electrode of the gate electrode film above the second region;
forming a second sidewall insulating film on a sidewall of the second gate electrode and above the second region;
forming a first source region and a first drain region on both sides of the first gate electrode above the first region;
forming a second source region and a second drain region on both sides of the second gate electrode above the second region; and
forming a third impurity region below the first impurity region of the semiconductor substrate, wherein an impurity concentration of the third impurity region is higher than an impurity concentration of the first channel region,
wherein:
a first transistor including the first impurity region, the third impurity region, the first channel region, the first gate insulating film, the first gate electrode, the first sidewall insulating film, the first source region and the first drain region;
a second transistor including the second impurity region, the second gate insulating film, the second gate electrode, the second sidewall insulating film, the second source region and the second drain region; and
the first transistor storing information by accumulating charge in the first sidewall insulating film.

12. The method according to claim 11 , further comprising forming a second channel region by the epitaxial growth above the second impurity region, wherein the second transistor further including the second channel region.

13. The method according to claim 12 , wherein an impurity concentration o

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Ema Taiji
• Yasuda Makoto
• Mizutani Kazuhiro

Classifications

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H01L23/528 Primary

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L29/42348

  Electricity · mapped topic

• H01L29/792

  Electricity · mapped topic