Electronic device including moat power metallization in trench

Patent metadata

Field	Value
Publication number	US-10014214-B2
Application number	US-201715593496-A
Country	US
Kind code	B2
Filing date	May 12, 2017
Priority date	Jun 8, 2015
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

First claim

What is claimed is:

1. A method of forming an electronic device, the method comprising:
forming a silicon-on-insulator (SOI) substrate;
defining first and second trenches in the SOI substrate;
patterning circuitry in an uppermost portion of the SOI substrate;
disposing at least first and second power metallization in-plane with or above the patterned circuitry and in the first and second trenches, respectively; and
depositing insulation to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

2. The method according to claim 1 , wherein the defining of the first and second trenches and the patterning each comprise etching.

3. The method according to claim 1 , wherein the patterning of the circuitry comprises:
patterning front end features; etching vias for metallization; and
disposing metallization in the etched vias.

4. The method according to claim 1 , wherein the disposing of the second power metallization comprises insulating the second power metallization from trench sidewalls.

5. The method according to claim 1 , wherein the depositing of the insulation comprises forming vias in the insulation at the second locations.

Assignees

• Globalfoundries Inc

Inventors

• Chang Josephine B
• Chang Leland
• Guillorn Michael A
• Lin Chung-Hsun
• Pyzyna Adam M

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/057 Primary

  by selectively depositing, e.g. by using selective CVD or plating · CPC title