Method of manufacturing dielectric layers of semiconductor structure

Patent metadata

Field	Value
Publication number	US-10014207-B2
Application number	US-201514813707-A
Country	US
Kind code	B2
Filing date	Jul 30, 2015
Priority date	Aug 16, 2013
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A method of filling a dielectric trench includes forming two adjacent conductors on a substrate, forming a dielectric layer over a surface of the conductors and the substrate, removing a portion of the dielectric layer, treating a top surface of the dielectric layer with phosphorous plasma, and repeating the forming the dielectric layer, the removing the portion of the dielectric layer, and the treating the top surface of the dielectric layer in a multi cycle fashion. A narrowest width of the dielectric trench between the two adjacent conductors is smaller than about 30 nm.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor structure, comprising:
forming a surface having a trench profile on a substrate;
depositing a silicate layer over the surface with an in-situ sputtering operation, the silicate layer comprising an overhang in proximity to a top of the trench profile upon a completion of the forming the dielectric layer;
etching the silicate layer with a fluorine-based etchant until the overhang is removed;
treating a top surface of the silicate layer with oxygen plasma; and
repeating the depositing, the etching, and the treating operations until the trench profile being filled with a plurality of silicate layers,
wherein a fluorine concentration in the plurality of silicate layers monotonically decreases from about 2 E20 atoms/cm 3 at a bottom of the trench profile to about 1 E20 atoms/cm 3 at a top of the trench profile.

2. The method of claim 1 , wherein etching the silicate layer comprises applying NF 3 etch.

3. The method of claim 1 , further comprising forming a liner between the surface and the silicate layer.

4. A method of manufacturing a dielectric structure, comprising:
forming a surface profile over a substrate, the surface profile being composed of a top surface of a conductor, a sidewall surface of the conductor, and a top surface of the substrate, wherein a bottom surface of the conductor is in direct contact with the top surface of the substrate;
forming a first spacer;
forming a liner over the first spacer;
depositing a dielectric layer over the surface profile;
in-situ sputtering the dielectric layer; and
treating a top surface of the dielectric layer with plasma, repeating the depositing, the in-situ sputtering, and the treating operations until the surface profile being filled with a plurality of dielectric layers;
wherein a fluorine concentration in the plurality of dielectric layers monotonically decreases from about 2 E20 atoms/cm 3 at a bottom of the surface profile to about 1 E20 atoms/cm 3 at a top of the surface profile.

5. The method of claim 4 , further comprising forming a second spacer over the first spacer.

6. The method of claim 4 , wherein the dielectric structure comprises an aspect ratio greater than about 2.4.

7. The method of claim 4 , wherein in-situ sputtering comprises removing a portion of the dielectric layer by argon ions.

8. The method of claim 4 , further comprising performing a fluorine ion etch before treating the top surface of the dielectric layer.

9. The method of claim 4 , wherein treating the top surface of the dielectric layer with plasma comprises applying phosphorous plasma.

10. A method of filling a dielectric trench, comprising:
forming two adjacent conductors on a substrate thereby obtaining a trench profile having a trench depth;
forming a dielectric layer over the trench profile with an in-situ sputtering operation, the dielectric layer comprising an overhang in proximity to a top of the trench profile upon a completion of the forming the dielectric layer;
removing at least the overhang of the dielectric layer with a fluorine-based etchant and rendering the dielectric layer to possess about one-sixth of the trench depth;
treating a top surface of the dielectric layer with phosphorous plasma, and
repeating the forming the dielectric layer, the removing at least the overhang of the dielectric layer, and the treating the top surface of the dielectric layer in a multi cycle fashion until the dielectric layer achieving the trench depth,
wherein a fluorine concentration in the dielectric layer achieving the trench depth monotonically decreases from about 2 E20 atoms/cm 3 at a bottom of the trench profile to about 1 E20 atoms/cm 3 at a top of the trench profile while a substantial constant phosphorous concentration being maintained throughout the dielectric layer achieving the trench depth.

11. The method of claim 10 , wherein removing the portion of the dielectric layer comprises applying an NF 3 etch.

12. The method of claim 10 , wherein treating the top surface of the dielectric layer with phosphorous plasma comprises;
applying a first radio frequency power to form the plasma; and
applying a second radio frequency power to accelerate the plasma,
wherein the first radio frequency power and the second radio frequency power are substantially in a same range.

13. The method of claim 12 , wherein the first radio frequency power is in a range of from about 1000 W to about 9000 W.

14. The method of claim 10 , wherein a narrowest width of the dielectric trench between the two adjacent conductors is smaller than about 30 nm.

15. The method of claim 10 , wherein the forming the dielectric layer comprises performing phosphorous-doped silicon glass deposition operation.

16. The method of claim 10 , wherein the in-situ sputtering operation comprises removing a portion of the dielectric layer by argon ions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Jia-You
• Lee Kung-Wei

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10P14/6924

  the material being halogen doped silicon oxides, e.g. FSG · CPC title

• H10P14/6923

  the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG · CPC title

• H10P14/6532

  by exposure to a plasma · CPC title