Method for realizing ultra-thin sensors and electronics with enhanced fragility

Patent metadata

Field	Value
Publication number	US-10014204-B2
Application number	US-201615207185-A
Country	US
Kind code	B2
Filing date	Jul 11, 2016
Priority date	Jul 11, 2016
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A method of fabricating ultra-thin semiconductor devices includes forming an array of semiconductor dielets mechanically suspended on a frame with at least one tether connecting each semiconductor dielet of the array of semiconductor dielets to the frame.

First claim

What is claimed is:

1. A semiconductor dielet comprising:
a substrate;
an active layer formed on an upper surface of the substrate and including active devices; and
one or more fragility enhancing features on a lower surface of the substrate and not extending fully through the dielet to the upper surface, the one or more fragility enhancing features being located so that when projected orthogonally onto the upper surface they would occupy a same area as the active devices, the one or more fragility enhancing features reducing mechanical strength of the dielet as compared to a substantially similar dielet lacking the one or more fragility enhancing features.

2. The semiconductor dielet of claim 1 , wherein the one or more fragility enhancing features include one or more of a trench and a cavity defined in the lower surface of the substrate.

3. The semiconductor dielet of claim 2 , included in a security tag.

4. The semiconductor dielet of claim 3 , configured to self-destruct responsive to the security tag being removed from an object to which the security tag had been secured.

5. The semiconductor dielet of claim 1 , further comprising a tether remnant coupled to and extending from an edge of the dielet.

6. The semiconductor dielet of claim 1 , wherein the one or more fragility enhancing features extend into only portions of the lower surface of the substrate.

7. A semiconductor dielet comprising:
a substrate;
an active layer formed on an upper surface of the substrate and including active devices; and
one or more fragility enhancing features formed on a lower surface of the substrate below the active layer and extending only partially through the substrate, the one or more fragility enhancing features reducing mechanical strength of the dielet as compared to a substantially similar dielet lacking the one or more fragility enhancing features.

8. The semiconductor dielet of claim 7 , wherein the one or more fragility enhancing features include one or more of a trench and a cavity defined in the lower surface of the substrate.

9. The semiconductor dielet of claim 7 , included in a security tag.

10. The semiconductor dielet of claim 9 , configured to self-destruct responsive to the security tag being removed from an object to which the security tag had been secured.

11. The semiconductor dielet of claim 7 , further comprising a tether remnant coupled to and extending from an edge of the dielet.

12. The semiconductor dielet of claim 7 , having a thickness of less than 10 micrometers.

13. The semiconductor dielet of claim 7 , wherein the one or more fragility enhancing features extend into only portions of the lower surface of the substrate.

Assignees

• Charles Stark Draper Laboratory Inc

Inventors

• Cook Eugene H
• Duwel Amy
• Carter David J
• Perlin Gayatri E

Classifications

• H10P72/7432

  used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate · CPC title

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title