Overcoming variance in stacked capacitors

Patent metadata

Field	Value
Publication number	US-10014123-B2
Application number	US-201615065631-A
Country	US
Kind code	B2
Filing date	Mar 9, 2016
Priority date	Dec 14, 2011
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

In one embodiment of the invention, a method of forming an energy storage device is described in which a porous structure of an electrically conductive substrate is measured in-situ while being electrochemically etched in an electrochemical etching bath until a predetermined value is obtained, at which point the electrically conductive substrate may be removed from the electrochemical etching bath. In another embodiment, a method of forming an energy storage device is described in which an electrically conductive porous structure is measured to determine the energy storage capacity of the electrically conductive porous structure. The energy storage capacity of the electrically conductive porous structure is then reduced until a predetermined energy storage capacity value is obtained.

First claim

What is claimed is:

1. An energy storage device comprising:
an electrically conductive porous structure;
wherein the electrically conductive porous structure includes a bulk capacitor region having a bulk surface area, and an array of trim capacitor regions separated from the bulk capacitor region, the array of trim capacitor regions including a plurality of different surface areas,
wherein the bulk capacitor region contains multiple channels and wherein each of the channels has an opening to a surface of the electrically conductive porous structure.

2. The energy storage device of claim 1 , wherein the electrically conductive porous structure is formed on a metal layer, wherein the metal layer comprises a bulk pad below the bulk capacitor region, an array of pads below the array of trim capacitor regions, and a plurality of traces connecting the array of pads to the bulk pad.

3. The energy storage device of claim 1 , further comprising a fuse electrically connected to at least one of the trim capacitor regions.

4. The energy storage device of claim 1 , wherein the energy storage device is packaged within an electronic device and is associated with a microprocessor.

5. An energy storage device comprising:
an electrically conductive porous structure;
wherein the electrically conductive porous structure comprises a bulk capacitor region having a bulk unit surface area, and at least one trim capacitor region in which the conductive porous structure is fused and has a reduced unit surface area,
wherein the bulk capacitor region contains multiple channels wherein each of the channels has an opening to a surface of the electrically conductive porous structure.

6. The energy storage device of claim 5 , wherein the trim capacitor region comprises a fused channel opening.

7. The energy storage device of claim 5 , further comprising a plurality of trim capacitor regions.

8. The energy storage device of claim 5 , further comprising a plurality of trim capacitor regions having a plurality of different widths spanning a surface of the electrically conductive porous structure.

9. The energy storage device of claim 5 , wherein the energy storage device is packaged within an electronic device and is associated with a microprocessor.

Assignees

• Hannah Eric C
• Pint Cary L
• Holzwarth Charles W
• Gustafson John L
• Intel Corp

Inventors

• Hannah Eric C
• Pint Cary L
• Holzwarth Charles W
• Gustafson John L

Classifications

• H01G11/14

  Arrangements or processes for adjusting or protecting hybrid or EDL capacitors (emergency protective circuit arrangements specially adapted for capacitors, and effecting automatic switching in the event of an undesired change from normal working conditions H02H7/16; emergency protective circuit arrangements for limiting excess current or voltages without disconnection H02H9/00) · CPC title

• H01G11/84

  Processes for the manufacture of hybrid or EDL capacitors, or components thereof · CPC title

• Y02E60/13

  Energy storage using capacitors · CPC title

• H01G11/12

  Stacked hybrid or EDL capacitors · CPC title

• H01G11/24 Primary

  characterised by structural features of the materials making up or comprised in the electrodes, e.g. form, surface area or porosity; characterised by the structural features of powders or particles used therefor · CPC title