Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10014058-B2
Application number	US-201615334042-A
Country	US
Kind code	B2
Filing date	Oct 25, 2016
Priority date	Jun 9, 2016
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A semiconductor device may include an insulating layer, a bulk pattern, a stack structure, and a channel pattern. A first trench may be formed in the insulating layer. A bulk pattern may be located in the first trench and includes a metal pattern and an electron hole source. The stack structure may be located on the insulating layer and includes conductive layers and insulating layers, which are alternately stacked. The channel pattern may penetrate the stack structure, and may be supplied with electron holes from the bulk pattern.

First claim

What is claimed is:

1. A semiconductor device comprising:
an insulating layer and a first trench formed in the insulating layer;
a bulk pattern located in the first trench, the bulk pattern including a metal pattern and an electron hole source;
a stack structure located on the insulating layer, the stack structure including conductive layers and insulating layers, which are alternately stacked; and
a channel pattern penetrating the stack structure, the channel pattern being supplied with electron holes from the bulk pattern.

2. The semiconductor device of claim 1 , wherein the electron hole source is a polysilicon pattern formed in the metal pattern, the polysilicon pattern including a P-type impurity.

3. The semiconductor device of claim 1 , further comprising a connecting layer interposed between the stack structure and the insulating layer, the connecting layer connecting the bulk pattern and the channel pattern to each other.

4. The semiconductor device of claim 3 , wherein the connecting layer includes:
a first connecting layer interposed between the insulating layer and the stack structure, the first connecting layer contacting the bulk pattern; and
a second connecting layer interposed between the first connecting layer and the stack structure, the second connecting layer contacting the channel pattern.

5. The semiconductor device of claim 4 , wherein the first connecting layer is a polysilicon layer including an N-type impurity, and the electron hole source is a polysilicon pattern including a P-type impurity.

6. The semiconductor device of claim 3 , wherein the connecting layer includes an impurity region contacting the electron hole source, the impurity region including a P-type impurity.

7. The semiconductor device of claim 1 , further comprising:
a second trench formed in the insulating layer, the second trench having a narrower width than the first trench; and
a source pattern formed in the second trench.

8. The semiconductor device of claim 7 , wherein the source pattern includes the same material as the metal pattern and is located at substantially the same level as the bulk pattern.

9. The semiconductor device of claim 7 , wherein the bulk pattern and the source pattern are insulated from each other by the insulating layer.

10. The semiconductor device of claim 7 , further comprising a circuit located under the insulating layer, the circuit being electrically connected to the source pattern.

11. The semiconductor device of claim 10 , wherein, in a read operation, the source pattern is grounded by the circuit.

12. The semiconductor device of claim 1 , wherein, in an erase operation, electron holes are supplied into the channel pattern from the electron hole source.

13. A semiconductor device comprising:
a bulk pattern located in an insulating layer, the bulk pattern including an electron hole source;
a source pattern located in the insulating layer;
a stack structure located on the insulating layer, the stack structure including conductive layers and insulating layers, which are alternately stacked;
a channel pattern penetrating the stack structure; and
a connecting layer interposed between the insulating layer and the stack structure, the connecting layer connecting the bulk pattern, the source pattern, and the channel pattern to each other.

14. The semiconductor device of claim 13 , wherein the bulk pattern includes a metal pattern and an electron hole source in the metal pattern, and the electron hole source is a polysilicon pattern including a P-type impurity.

15. The semiconductor device of claim 14 , wherein the metal pattern and the source pattern include the same material, and the source pattern and the bulk pattern are located at substantially the same level as each other.

16. The semiconductor device of claim 13 , wherein the bulk pattern has a wider width than the source pattern.

17. The semiconductor device of claim 13 , wherein the connecting layer includes:
a first connecting layer contacting the bulk pattern and the source pattern; and
a second connecting layer interposed between the first connecting layer and the stack structure, the second connecting layer contacting the channel pattern.

18. The semiconductor device of claim 13 , further comprising a circuit located under the insulating layer, the circuit being electrically connected to the source pattern.

19. The semiconductor device of claim 18 , wherein, in a read operation, the source pattern is grounded by the circuit.

20. The semiconductor device of claim 13 , wherein, in an erase operation, electron holes are supplied into the channel pattern from the electron hole source.

Assignees

• Sk Hynix Inc

Inventors

• Lee Nam Jae

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/5226

  Electricity · mapped topic

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title