Storage module and method for scheduling memory operations for peak-power management and balancing

Patent metadata

Field	Value
Publication number	US-10013345-B2
Application number	US-201414489179-A
Country	US
Kind code	B2
Filing date	Sep 17, 2014
Priority date	Sep 17, 2014
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A storage module and method for scheduling memory operations for peak-power management and balancing are provided. In one embodiment, a storage module maintains a count of time slots over a period of time. The period of time corresponds to an amount of time between periodic power peaks of a memory operation. For each time slot, the storage module determines whether to commence a memory operation on one or more of the plurality of memory dies based on whether a power peak generated in the time slot by the memory operation would exceed a power threshold allowed for the time slot. Other embodiments are provided.

First claim

What is claimed is:

1. A method for scheduling a memory operation, the method comprising:
performing the following in a memory die in a storage module having a plurality of memory dies:
maintaining a count of time slots over a period of time, wherein the period of time corresponds to an amount of time between periodic power peaks of a memory operation, wherein each of the plurality of memory dies is assigned a different one of the time slots in which to have a power peak;
determining whether to commence a memory operation in the memory die in a current time slot based on whether commencing the memory operation in the current time slot will cause a power peak of the memory operation to occur in the time slot assigned to the memory die, wherein the power peak of the memory operation occurs a predetermined number of time slots after commencement of the memory operation;
in response to determining to commence the memory operation in the memory die in the current time slot, commencing the memory operation in the memory die; and
in response to determining not to commence the memory operation in the memory die in the current time slot, delaying commencement of the memory operation until a later time slot to cause the power peak of the memory operation to occur in the time slot assigned to the memory die;
wherein because each of the memory dies is assigned a different one of the time slots in which to have a power peak, power peaks are distributed over time to reduce a probability of multiple power peak consumption alignment.

2. The method of claim 1 further comprising tracking power consumed by memory operations performed across the plurality of memory dies.

3. The method of claim 2 further comprising incrementing the tracked power when the memory operation commences.

4. The method of claim 2 further comprising decrementing the tracked power when the memory operation is completed.

5. The method of claim 1 , wherein the memory operation comprises an erase operation.

6. The method of claim 1 , wherein at least one of the memory dies comprises a three-dimensional memory.

7. The method of claim 1 , wherein the storage module is embedded in a host.

8. The method of claim 1 , wherein the storage module is removably connected to a host.

9. The method of claim 1 , wherein the storage module is a solid-state drive.

10. A storage module comprising:
a plurality of memory dies;
means for maintaining a count of time slots over a period of time, wherein the period of time corresponds to an amount of time between periodic power peaks of a memory operation, wherein each of the plurality of memory dies is assigned a different one of the time slots in which to have a power peak; and
means for determining whether to commence a memory operation in a memory die in a current time slot based on whether commencing the memory operation in the current time slot will cause a power peak of the memory operation to occur in the time slot assigned to the memory die, wherein the power peak of the memory operation occurs a predetermined number of time slots after commencement of the memory operation;
means for, in response to determining to commence the memory operation in the memory die in the current time slot, commencing the memory operation in the memory die; and
means for, in response to determining not to commence the memory operation in the memory die in the current time slot, delaying commencement of the memory operation until a later time slot to cause the power peak of the memory operation to occur in the time slot assigned to the memory die;
wherein because each of the memory dies is assigned a different one of the time slots in which to have a power peak, power peaks are distributed over time to reduce a probability of multiple power peak consumption alignment.

11. The storage module of claim 10 further comprising means for tracking power consumed by memory operations performed across the plurality of memory dies.

12. The storage module of claim 11 further comprising means for incrementing the tracked power when the memory operation commences.

13. The storage module of claim 11 further comprising means for decrementing the tracked power when the memory operation is completed.

14. The storage module of claim 10 , wherein the memory operation comprises an erase operation.

15. The storage module of claim 10 , wherein at least one of the memory dies comprises a three-dimensional memory.

16. The storage module of claim 10 , wherein the storage module is embedded in a host.

17. The storage module of claim 10 , wherein the storage module is removably connected to a host.

18. The storage module of claim 10 , wherein the storage module is a solid-state drive.

19. A storage module comprising:
a plurality of memory dies; and
a controller;
wherein each of the memory dies is configured to:
maintain a count of time slots over a period of time, wherein the period of time corresponds to an amount of time between periodic power peaks of a memory operation, wherein each of the plurality of memory dies is assigned a different one of the time slots in which to have a power peak; and
determine whether to start a memory operation in a memory die in an active time slot based on whether starting the memory operation in the active time slot will cause a power peak of the memory operation to occur in the time slot assigned to the memory die, wherein the power peak of the memory operation occurs a predetermined number of time slots after starting the memory operation;

in response to determining to start the memory operation in the memory die in the active time slot, start the memory operation in the memory die in the active time slot; and
in response to determining not to start the memory operation in the memory die in the active time slot, delay starting the memory operation until a later active time slot to cause the power peak of the memory operation to occur in the time slot assigned to the memory die;
wherein because each of the memory dies is assigned a different one of the time slots in which to have a power peak, power peaks are distributed over time to reduce a probability of multiple power peak consumption alignment.

20. The storage module of claim 19 , wherein the controller is configured to assign a time slot to each memory die.

21. The storage module of claim 19 , wherein the controller is configured to send an indication of an active time slot to the plurality of memory dies.

22. The storage module of claim 19 , wherein at least one of the memory dies comprises a three-dimensional memory.

23. The storage module of claim 19 , wherein the storage module is embedded in a host.

24. The storage module of claim 19 , wherein the storage module is removably connected to a host.

25. The storage module of claim 19 , wherein the storage module is a solid-state drive.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Erez Eran
• Hsu Cynthia

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic

• G06F3/0625 Primary

  Power saving in storage systems · CPC title

• G11C16/30

  Power supply circuits · CPC title