Control mechanism based on timing information

Patent metadata

Field	Value
Publication number	US-10013295-B2
Application number	US-201414899548-A
Country	US
Kind code	B2
Filing date	Jun 17, 2014
Priority date	Jun 18, 2013
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

There is provided an apparatus comprising thresholding means adapted to check if an average frequency of occurrence of timing violations is outside a range; and controlling means adapted to control at least one of a clock frequency, a processing, a heat generation, a bias voltage, a current, and a temperature in a direction to bring the average frequency of occurrence of timing violations into the range if the average frequency of occurrence of timing violations is outside the range.

First claim

The invention claimed is:

1. A logic circuit apparatus comprising
a logic circuit pipeline adapted to be clocked by a clock frequency, to process a process, and to work at a temperature, wherein the logic pipeline comprises at least two combinational logic units and a corresponding number of registers, wherein each combinational logic unit has at least one input terminal and at least one output terminal, and wherein each of the registers is connected to an output terminal of one of the combinational logic units;
a hardware timing violation detector coupled to the logic pipeline and adapted to detect a timing violation occurring in at least one of the at least two combinational logic units;
a timing violation frequency collector coupled to the timing violation detector and adapted to obtain an average frequency of occurrence of timing violations in the logic pipeline, based on the detection by the timing violation detector;
thresholding detector adapted to check if the average frequency of occurrence of timing violations is outside a range;
a trigger adapted to provide a trigger signal if the average frequency of occurrence of timing violations is outside the range; and
a controller responsive to the trigger and adapted to control at least one of the clock frequency, a processing of the process, heat generation, a bias voltage, a current, and the temperature in a direction to bring the average frequency of occurrence of timing violations into the range if the average frequency of occurrence of timing violations is outside the range;
wherein the timing violation frequency collector is further adapted to adapt a period for obtaining the average timing violation frequency according to a period dependency function based on at least one of the processing, the temperature, a supply voltage and data to be processed.

2. The apparatus according to claim 1 further comprising
an obtaining receptor adapted to obtain a value of an average frequency of occurrence of timing violations.

3. The apparatus according to claim 1 wherein
the logic pipeline comprises at least two combinational logics and a corresponding number of registers, wherein each of the registers is connected to an output terminal of one of the combinational logics, and the apparatus further comprises
a timing violation detector adapted to detect a timing violation occurring in at least one of the at least two combinational logics; wherein
the timing violation frequency collector is adapted to obtain the average frequency of occurrence of timing violations based on the detection by the timing violation detector.

4. The apparatus according to claim 1 wherein
the logic pipeline comprises at least two combinational logics and a corresponding number of registers, wherein each of the registers is connected to an output terminal of one of the combinational logics, and the apparatus further comprises
at least two timing violation frequency detectors adapted to obtain the average frequency of occurrence of timing violations separately for each of the at least two combinational logics.

5. The apparatus according to claim 1 wherein
the thresholding detector is further adapted to retrieve the range from a range dependency function based on at least one of the clock frequency, the processing, the heat generation, the bias voltage, the current, the temperature, the supply voltage and data to be processed.

6. The apparatus according to claim 1 wherein at least one of the thresholding detector, trigger, logic pipeline and timing violation frequency collector is implemented as a hardware.

7. A method comprising
operating a logic circuit pipeline comprising at least two combinational logic units and a corresponding number of registers, wherein each of the registers is connected to an output terminal of one of the combinational logic units, and wherein logic pipeline is clocked by a clock frequency, processes a process, and works at a temperature;
detecting a timing violation with a hardware timing violation detector occurring in at least one of the two combinational logic units;
obtaining an average frequency of occurrence of timing violations in the logic pipeline;
checking if the average frequency of occurrence of timing violations is outside a range;
providing a trigger if the average frequency of occurrence of timing violations is outside the range;
controlling, responsive to the trigger, at least one of the clock frequency, the processing, heat generation, a bias voltage, a current, and the temperature in a direction to bring the average frequency of occurrence of timing violations into the range if the average frequency of occurrence of timing violations is outside the range; and
adapting a period for obtaining the average timing violation frequency according to a period dependency function based on at least one of the processing, the temperature, a supply voltage and data to be processed.

8. A non-transient computer readable medium containing computer program instructions which, when executed on an apparatus, cause the apparatus to:
obtain an average frequency of occurrence of timing violations in a logic circuit pipeline comprising at least two combinational logic units and a corresponding number of registers, wherein each of the registers is connected to an output terminal of one of the combinational logic units, wherein the logic pipeline is clocked by a clock frequency, processing a process, and working at a temperature;
detect a timing violation occurring in at least one of the two combinational logics;
check if the average frequency of occurrence of timing violations is outside a range;
provide a trigger if the average frequency of occurrence of timing violations is outside the range;
control, responsive to the trigger, at least one of the clock frequency, the processing, heat generation, a bias voltage, a current, and the temperature in a direction to bring the average frequency of occurrence of timing violations into the range if the average frequency of occurrence of timing violations is outside the range; and
adapt a period for obtaining the average timing violation frequency according to a period dependency function based on at least one of the processing, the temperature, a supply voltage and data to be processed.

Assignees

• Aalto Univ Foundation
• Teknologian Tutkimuskeskus Vtt Oy
• Minima Processor Oy

Inventors

• Mäkipää Jani
• Koskinen Lauri
• Turnquist Matthew
• Hiienkari Markus

Classifications

• G06F1/14 Primary

  Time supervision arrangements, e.g. real time clock · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• H03K5/13

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F11/0757 Primary

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title