Low voltage regulator

Patent metadata

Field	Value
Publication number	US-10013005-B1
Application number	US-201715693028-A
Country	US
Kind code	B1
Filing date	Aug 31, 2017
Priority date	Aug 31, 2017
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

Apparatus and method relating to voltage regulation is disclosed. In an apparatus thereof, an integrated circuit includes a first differential opamp having a first gain. The first differential opamp is configured to receive a reference voltage and a feedback voltage. A second differential opamp has a second gain less than the first gain. The second differential opamp is configured to receive the reference voltage and the feedback voltage. A driver transistor is configured to provide an output voltage at an output voltage node and to receive a gating voltage output from the second differential opamp. A differential output of the first differential opamp is configured for gating a current source transistor of the second differential opamp. A capacitor is connected to the driver transistor and the current source transistor.

First claim

What is claimed is:

1. An integrated circuit for voltage regulation, comprising:
a first differential opamp having a first gain configured to receive a reference voltage and a feedback voltage;
a second differential opamp having a second gain less than the first gain configured to receive the reference voltage and the feedback voltage;
a driver transistor configured to provide an output voltage at an output voltage node and to receive a gating voltage output from the second differential opamp;
a differential output of the first differential opamp configured for gating a current source transistor of the second differential opamp; and
a capacitor connected to the driver transistor and the current source transistor.

2. The integrated circuit according to claim 1 , further comprising a resistor coupled between an output node of the first differential opamp and a gate node of the current source transistor.

3. The integrated circuit according to claim 1 , wherein the capacitor is connected to a gate node of the driver transistor and a drain node of the current source transistor.

4. The integrated circuit according to claim 3 , further comprising a resistor coupled between an output node of the first differential opamp and a gate node of the current source transistor.

5. The integrated circuit according to claim 4 , further comprising a high pass filter coupled between the output node of the first differential opamp and a ground bus.

6. The integrated circuit according to claim 5 , further comprising a self-bias circuit configured to provide a bias voltage to the first differential opamp.

7. The integrated circuit according to claim 5 , wherein the first gain is at least a factor of times 80 greater than the second gain.

8. The integrated circuit according to claim 5 , further comprising a resistor ladder connected between the output voltage node and the ground bus and configured to provide the feedback voltage as a fraction of the output voltage.

9. The integrated circuit according to claim 5 , wherein the output voltage is the feedback voltage.

10. The integrated circuit according to claim 5 , wherein the driver transistor is a multigate transistor.

11. The integrated circuit according to claim 5 , wherein the current source transistor is a multigate transistor.

12. The integrated circuit according to claim 5 , wherein the first differential opamp is a differential folded cascode opamp.

13. The integrated circuit according to claim 12 , wherein the second differential opamp is a single stage differential opamp.

14. A method for voltage regulation, comprising:
receiving a reference voltage and a feedback voltage by a first differential opamp having a first gain;
receiving the reference voltage and the feedback voltage by a second differential opamp having a second gain less than the first gain;
generating by a driver transistor an output voltage at an output voltage node, the generating comprising:
receiving by the driver transistor a gating voltage output from the second differential opamp; and
supplying a load current across a channel of the driver transistor for a drain node of the driver transistor connected to the output voltage node to provide the output voltage;

gating a current source transistor of the second differential opamp responsive to a differential output of the first differential opamp; and
dampening the gating voltage at a gate node of the driver transistor with a capacitor connected between the gate node of the driver transistor and a drain node of the current source transistor.

15. The method according to claim 14 , wherein the dampening comprises putting the capacitor in a low impedance state responsive to a frequency component in the output voltage being greater than 100 kilohertz.

16. The method according to claim 15 , wherein the output voltage is in a range of 0.8 to 1.2 volts, and wherein the load current is in a range of 3 to 25 milliamps.

17. The method according to claim 15 , wherein the dampening is first dampening, the method further comprising:
second dampening the gating voltage at the gate node of the driver transistor with a resistor connected between an output node of the first differential opamp and a gate node of the current source transistor.

18. The method according to claim 17 , wherein the second dampening is responsive to the frequency component in the output voltage being less than 100 kilohertz.

19. The method according to claim 14 , further comprising reducing the output voltage to a fraction thereof to provide as the feedback voltage.

20. The method according to claim 14 , further comprising:
generating a bias voltage with a self-bias circuit; and
biasing the first differential opamp with the bias voltage.

Assignees

• Xilinx Inc

Inventors

• Ippili Sharat Babu

Classifications

• G05F1/575

  characterised by the feedback circuit · CPC title

• G05F1/461 Primary

  using an operational amplifier as final control device · CPC title

• G05F1/468

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title