Three-dimensional integrated photonic structure with improved optical properties

Patent metadata

Field	Value
Publication number	US-10012792-B2
Application number	US-201615217100-A
Country	US
Kind code	B2
Filing date	Jul 22, 2016
Priority date	Jan 8, 2016
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

An integrated electronic device includes a substrate having an opening extending therethrough. The substrate includes an interconnection network, and connections coupled to the interconnection network. The connections are to be fixed on a printed circuit board. An integrated photonic module is electrically connected to the substrate, with a portion of the integrated photonic module in front of or overlapping the opening of the substrate. An integrated electronic module is electrically connected to the photonic module, and extends at least partly into the opening of the substrate. The electronic module and the substrate may be electrically connected onto the same face of the photonic module.

First claim

That which is claimed is:

1. An integrated device comprising:
a substrate having an opening extending therethrough and comprising an interconnection network, and a plurality of connections coupled to said interconnection network;
an integrated photonic module electrically coupled to said substrate, with a portion of said integrated photonic module overlapping the opening of said substrate;
an integrated electronic module electrically coupled to said integrated photonic module and extending at least partly into the opening of said substrate, wherein said integrated electronic module and said substrate are electrically coupled to a same side of said integrated photonic module; and
a heat sink coupled to said integrated electronic module, wherein said heat sink is configured so that when said substrate is coupled to a printed circuit board via said plurality of connections, said heat sink is also in contact with the printed circuit board.

2. The integrated device according to claim 1 , wherein said plurality of connections is arranged on a first side of said substrate; and wherein said integrated photonic module is coupled to a second side of said substrate opposite the first side.

3. The integrated device according to claim 2 , wherein said integrated photonic module comprises:
a semiconductor layer adjacent the second side of said substrate and overlapping the opening of said substrate, and
a plurality of photonic components incorporated within said semiconductor layer, wherein said plurality of photonic components comprises at least one first optical coupler non-overlapping the opening of said substrate.

4. The integrated device according to claim 3 , wherein said plurality of photonic components further comprises a second optical coupler non-overlapping the opening of said substrate.

5. The integrated device according to claim 3 , wherein said plurality of photonic components further comprises a second optical coupler overlapping the opening of said substrate.

6. A method for making an integrated device comprising:
providing a substrate having an opening extending therethrough, with the substrate comprising an interconnection network and a plurality of connections coupled to the interconnection network;
coupling a photonic module to the substrate, with a portion of the photonic module overlapping the opening of the substrate;
coupling an electronic module to the photonic module, with the electronic module extending at least partly into the opening of the substrate, wherein the electronic module and the substrate are coupled to a same side of the photonic module; and
coupling a heat sink to the electronic module, wherein the heat sink is configured so that when the substrate is coupled to a printed circuit board via the plurality of connections, the heat sink is also in contact with the printed circuit board.

7. The method according to claim 6 , wherein the plurality of connections are arranged on a first side of the substrate, and wherein the photonic module is coupled to a second side of the substrate opposite the first side.

8. The method according to claim 7 , wherein the photonic module comprises a semiconductor layer adjacent the second side of the substrate and overlapping the opening of the substrate, and a plurality of photonic components incorporated within the semiconductor layer, with the plurality of photonic components comprising at least one first optical coupler non-overlapping the opening of the substrate.

9. The method according to claim 8 , wherein the plurality of photonic components further comprises a second optical coupler non-overlapping the opening of the substrate.

10. The method according to claim 8 , wherein the plurality of photonic components further comprises a second optical coupler overlapping the opening of the substrate.

11. An integrated device comprising:
a substrate having a first major surface and a second major surface, the substrate comprising a hole extending from the first major surface to the second major surface and an interconnection network;
a plurality of balls attached to the first major surface and electrically coupled to the interconnection network;
a photonic chip attached to the first major surface and electrically coupled to the interconnection network, wherein a portion of the photonic chip overlaps with the hole; and
an integrated circuit chip for controlling the photonic chip disposed in the hole and electrically coupled to the photonic chip,
wherein the integrated circuit chip and the substrate are attached to a same side of the photonic chip.

12. The integrated device according to claim 11 , wherein the photonic chip is attached to the first major surface through a plurality of pillars.

13. The integrated device according to claim 11 , wherein the integrated circuit chip is attached to the photonic chip through a plurality of pillars.

14. The integrated device according to claim 11 , wherein the photonic chip has a larger footprint than the integrated circuit chip.

15. The integrated device according to claim 11 , wherein the photonic chip comprises:
a semiconductor layer adjacent the first major surface of the substrate and overlapping the hole, and
a plurality of photonic components disposed within the semiconductor layer, wherein the plurality of photonic components comprise a first optical coupler overlapping the hole.

16. The integrated device according to claim 15 , wherein the plurality of photonic components further comprises a second optical coupler not overlapping with the hole.

17. The integrated device according to claim 15 , wherein the plurality of photonic components further comprises a second optical coupler overlapping with the hole.

18. The integrated device according to claim 11 , further comprising a heat sink coupled to the integrated circuit chip.

19. The integrated device according to claim 11 , wherein the substrate is configured to be mounted to a printed circuit board through the plurality of balls.

20. A method for making an integrated device comprising:
providing a substrate having a first major surface and a second major surface, the substrate comprising a hole extending from the first major surface to the second major surface and an interconnection network;
forming a plurality of balls attached to the first major surface and electrically coupled to the interconnection network;
attaching a photonic chip to the first major surface and electrically coupled to the interconnection network, wherein a portion of the photonic chip overlaps with the hole; and
electrically coupling an integrated circuit chip for controlling the photonic chip to the photonic chip, the integrated circuit chip disposed in the hole, wherein the integrated circuit chip and the substrate are attached to a same side of the photonic chip.

21. The method according to claim 20 , wherein attaching a photonic chip to the first major surface comprises attaching the photonic chip to the first major surface through a plurality of pillars.

22. The method according to claim 20 , further comprising attaching the integrated circuit chip to the photonic chip through a plurality of pillars.

23. The method according to claim 20 , wherein the photonic chip has a larger footprint than the integrated circuit chip.

24. The method according to claim 20 , wherein the photonic chip comprises:
a semiconductor layer adjacent the first major surface of the substrate and overlapping the

Assignees

• St Microelectronics Crolles 2 Sas

Inventors

• Carpentier Jean-Francois
• Lemaitre Patrick
• Fourel Mickael

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• G02B6/428

  containing printed circuit boards [PCB] · CPC title

• G02B6/30

  for use between fibre and thin-film device · CPC title