Methods and systems for board level photonic bridges

Patent metadata

Field	Value
Publication number	US-10009668-B2
Application number	US-201514955142-A
Country	US
Kind code	B2
Filing date	Dec 1, 2015
Priority date	Dec 1, 2014
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

As photonics evolves closer and closer to the electronic processing elements in order to meet the demands of speed, latency of evolving data communications networks and data centers the inventors, rather than seeking direct monolithically integrated CMOS based processing photonic and electronic elements, have established a different route. Namely replace the computer hubs/electrical bridges interconnecting the multiple core logic chipset elements with a photonic bridge. In this manner high risk chip-to-chip photonic point-to-point links are replaced with photonic SOCs that leverage photonics bandwidth density attribute rather than its bandwidth distance attributes. An SOI based Electronic Embedded Photonic Switching Fabric is presented supporting, for example, N×MGb/s interconnections exploiting N channels of MGb/s wherein each channel of exploits S WDM channels of TGb/s. Embodiments of the invention also support high density optical interconnection via vertical grating couplers and multicore fibers.

First claim

What is claimed is:

1. A device for interconnecting a plurality of N electronic server elements of a server blade, the device comprising;
a monolithic photonic circuit provided within the server blade, the monolithic photonic circuit incorporating an N×N optical switch wherein,
each input port of the N×N optical switch being coupleable to a corresponding one of the plurality of N electronic server elements within the server blade;
each output port of the N×N optical switch being coupleable to a corresponding one of the plurality of N electronic server elements within the server blade;
the monolithic photonic circuit incorporating a plurality of electro-optic (E/O) arrays, a plurality of channel wavelength multiplexers, and at least one optical detector;
the input ports of the N×N optical switch being coupleable to corresponding ones of the plurality of N electronic circuits via corresponding ones of the plurality of electro-optic arrays and corresponding ones of the plurality of channel wavelength multiplexers, each E/O array generating a plurality of wavelengths multiplexed to each other via a corresponding one of the plurality of channel wavelength muitiplexers; and
each of the output ports of the N×N optical switch being coupleable to the corresponding one of the plurality of N electronic circuits via the at least one optical detector;
wherein the E/O arrays generate the plurality of wavelengths offset relative to each other in time, the at least one optical detector being provided in the form of a broadband detector for detecting the plurality of wavelengths offset relative to each other in time.

Assignees

• The Royal Institution For The Advancement Of Learning/ Mcgill Univ
• The Royal Institution For The Advancement Of Learning / Mcgill Univ

Inventors

• Liboiron-Ladouceur Odile
• Hai Md Shafiqul
• Pour Fard Monireh Moayedi
• Zhang Chunshu
• Sakib Meer

Classifications

• H04Q2011/0028

  using holograms · CPC title

• H04B10/801

  using optical interconnects, e.g. light coupled isolators, circuit board interconnections · CPC title

• H04Q2011/0022

  using fibre gratings · CPC title

• H04Q2011/005

  Arbitration and scheduling · CPC title

• H04Q11/0005 Primary

  Switch and router aspects · CPC title