Circuit and method to generate frequency proportional current

Patent metadata

Field	Value
Publication number	US-10009019-B2
Application number	US-201615282957-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

Disclosed examples include self-biased DLL circuits to generate a bias current signal proportional to a repetition frequency of a first signal representing continuous switching or discontinued switching operation of the DC-DC converter. The DLL circuit includes a monostable multivibrator to provide a pulse output signal in response to an edge of the first signal with a pulse duration set by a control current signal, a phase detector to provide output signals according to a phase difference between an edge of the pulse output signal and the first signal, and an output circuit to provide an output signal according to the phase detector output signals and according to an offset signal, to provide the bias current signal according to the output signal, and to provide the control current signal according to the output signal.

First claim

The following is claimed:

1. A power conversion system, comprising:
a DC-DC converter circuit, including:
a first switching device coupled between a DC input node and a switching node, the first switching device operative according to a first switching control signal, and
a second switching device coupled between the switching node and a reference voltage node, the second switching device operative according to a second switching control signal;

a control circuit, including:
first and second driver outputs to provide the first and second switching control signals according to a feedback signal to regulate an output voltage signal of the DC-DC converter circuit,
a bias current input to receive a bias current signal to operate a component of the control circuit, and
a signal output to provide a first signal having a first state representing continuous switching operation of the DC-DC converter circuit and a second state representing discontinued switching operation of the DC-DC converter circuit; and

a self-biased delay lock loop (DLL) circuit to generate the bias current signal proportional to a repetition frequency of the first signal.

2. The power conversion system of claim 1 , wherein the DLL circuit includes:
a monostable multivibrator circuit to provide a pulse output signal in response to a detected edge of the first signal, the monostable multivibrator circuit linearly controlling a pulse duration of the pulse output signal according to a control current signal;
a phase detector circuit to provide first and second phase detector output signals according to a phase difference between an edge of the pulse output signal and the first signal; and
an output circuit to provide an output signal according to the first and second phase detector output signals and according to an offset signal, to provide the bias current signal according to the output signal, and to provide the control current signal according to the output signal.

3. The power conversion system of claim 2 , wherein the output circuit includes:
a capacitor connected to a control node to provide the output signal as a control voltage output signal at the control node;
a charge pump circuit configured to selectively source a first current to the control node when the first phase detector output signal is in a first state, to selectively sink a second current from the control node when the second phase detector output signal is in a first state;
a current sink circuit to provide the offset signal by sinking a third current from the control node;
a voltage to current converter circuit to generate an output current signal proportional to the control voltage output signal; and
a current mirror circuit coupled with the voltage to current converter circuit to generate the bias current signal proportional to the output current signal, and to provide the control current signal proportional to the output current signal to the control input of the monostable multivibrator circuit to control the pulse duration of the output pulse signal.

4. The power conversion system of claim 3 ,
wherein the charge pump circuit includes:
a first switching circuit to selectively connect a first output of the current mirror circuit to the control node to source the first current to the control node when the first phase detector output signal is in the first state, and
a second switching circuit to selectively connect a second output of the current mirror circuit to the control node to sink the second current from the control node when the second phase detector output signal is in the first state; and

wherein the current sink circuit is a third output of the current mirror circuit connected to the control node to sink the third current from the control node.

5. The power conversion system of claim 4 , wherein the first current is equal to the second current; and wherein the third current is half the first current.

6. The power conversion system of claim 3 , wherein the first current is equal to the second current; and wherein the third current is half the first current.

7. An integrated circuit (IC) to operate a DC-DC converter circuit, the IC comprising:
a control circuit, including:
a driver circuit to provide a switching control signal to operate a switch of the DC-DC converter circuit according to a feedback signal to regulate an output voltage signal of the DC-DC converter circuit,
a bias current input to receive a bias current signal to operate a component of the control circuit, and
a signal output to provide a first signal having a first state representing continuous switching operation of the DC-DC converter circuit and a second state representing discontinued switching operation of the DC-DC converter circuit; and

a self-biased delay lock loop (DLL) circuit to generate the bias current signal proportional to a repetition frequency of the first signal.

8. The IC of claim 7 , wherein the DLL circuit includes:
a monostable multivibrator circuit to provide a pulse output signal in response to a detected edge of the first signal, the monostable multivibrator circuit linearly controlling a pulse duration of the pulse output signal according to a control current signal;
a phase detector circuit to provide first and second phase detector output signals according to a phase difference between an edge of the pulse output signal and the first signal; and
an output circuit to provide an output signal according to the first and second phase detector output signals and according to an offset signal, to provide the bias current signal according to the output signal, and to provide the control current signal according to the output signal.

9. The IC of claim 8 , wherein the output circuit includes:
a capacitor connected to a control node to provide the output signal as a control voltage output signal at the control node;
a charge pump circuit configured to selectively source a first current to the control node when the first phase detector output signal is in a first state, to selectively sink a second current from the control node when the second phase detector output signal is in a first state;
a current sink circuit to provide the offset signal by sinking a third current from the control node;
a voltage to current converter circuit to generate an output current signal proportional to the control voltage output signal; and
a current mirror circuit coupled with the voltage to current converter circuit to generate the bias current signal proportional to the output current signal, and to provide the control current signal proportional to the output current signal to the control input of the monostable multivibrator circuit to control the pulse duration of the output pulse signal.

10. The IC of claim 9 ,
wherein the charge pump circuit includes:
a first switching circuit to selectively connect a first output of the current mirror circuit to the control node to source the first current to the control node when the first phase detector output signal is in the first state, and
a second switching circuit to selectively connect a second output of the current mirror circuit to the control node to sink the second current from the control node when the second phase detector output signal is in the first state; and

wherein the current sink circuit is a third output of the current mirror circuit connected to the control node to sink the third current from the control node.

11. The IC of claim 10 , wherein the first current is equal to the second current; and wherein the third current is half the first current.

12. The IC of claim 9 , wherein the first current is equal to the second current; and wherein the th

Assignees

• Texas Instruments Inc

Inventors

• Couleur Michael
• Gibson Neil
• Priego Antonio

Classifications

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03K4/52

  using two semiconductor devices so coupled that the input of each one is derived from the output of the other, e.g. multivibrator · CPC title

• H03K7/06 Primary

  Frequency or rate modulation, i.e. PFM or PRM · CPC title

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title

• H03L7/089

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title