Semiconductor device having silicon-germanium source/drain regions with varying germanium concentrations

Patent metadata

Field	Value
Publication number	US-10008600-B2
Application number	US-201715685459-A
Country	US
Kind code	B2
Filing date	Aug 24, 2017
Priority date	Jul 22, 2014
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a device isolating layer embedded within the semiconductor substrate and defining an active region;
a channel region formed in the active region;
a gate electrode disposed above the channel region;
a gate insulating layer provided between the channel region and the gate electrode;
a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration and higher than the first concentration; and
a contact plug disposed on the silicon germanium epitaxial layer,
wherein the contact plug extends into the third epitaxial layer, and
wherein the first to third epitaxial layers are sequentially stacked on one another in that order and the third epitaxial layer is the uppermost layer of the silicon germanium epitaxial layer.

2. The semiconductor device of claim 1 , wherein the silicon germanium epitaxial layer further includes a buffer epitaxial layer having a germanium concentration lower than the first concentration, below the first epitaxial layer.

3. The semiconductor device of claim 2 , wherein the germanium concentration of the buffer epitaxial layer is in a range of 10 at % to 25 at %.

4. The semiconductor device of claim 2 , wherein the silicon germanium epitaxial layer may further include:
a first interfacial layer between the buffer epitaxial layer and the first epitaxial layer;
a second interfacial layer between the first epitaxial layer and the second epitaxial layer; and
a third interfacial layer between the second epitaxial layer and the third epitaxial layer.

5. The semiconductor device of claim 1 , wherein the first concentration is in a range of 25 at % to 50 at %, the second concentration is in a range of 50 at % to 90 at %, and the third concentration is in a range of 25 at % to 50 at %.

6. The semiconductor device of claim 1 , further comprising:
a metal silicide layer disposed between the silicon germanium epitaxial layer and the contact plug,
wherein the metal silicide layer is positioned in an upper portion of the second epitaxial layer.

7. The semiconductor device of claim 1 , wherein the silicon germanium epitaxial layer is doped with a p-type impurity and a concentration of the p-type impurity is varied in the first, second and third epitaxial layers in proportion to the first, second and third concentrations, respectively.

8. The semiconductor device of claim 7 , wherein the p-type impurity is boron.

9. The semiconductor device of claim 1 , wherein the active region includes a recessed region in a location corresponding to both sides of the gate electrode, and the silicon germanium epitaxial layer is formed in the recessed region of the active region.

10. The semiconductor device of claim 1 ,
wherein the active region includes a plurality of active layers, and the device isolating layer is provided to fill a space between the plurality of active layers to a predetermined height, and
wherein a width of the active region is reduced in an upward direction and an upper portion of the active region protrudes upwardly above the device isolating layer.

11. The semiconductor device of claim 10 , wherein the gate electrode is extended to cross the active region and cover the upper portion of the active region protruding upwardly above the device isolating layer.

12. The semiconductor device of claim 1 , wherein the gate insulating layer includes at least one high-k dielectric layer and the gate electrode is at least comprised of one of metal silicide and a metal.

13. The semiconductor device of claim 1 , wherein the semiconductor substrate is a monocrystalline, silicon substrate, and the active region is doped with an n-type impurity.

14. The semiconductor device of claim 1 , wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate, and the active region is doped with an n-type impurity.

15. A semiconductor device comprising:
a semiconductor substrate;
a device isolating layer embedded within the semiconductor substrate and defining an active region;
a channel region formed in the active region;
a gate electrode disposed above the channel region;
a gate insulating layer provided between the channel region and the gate electrode;
a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration and higher than the first concentration; and
a silicon capping layer and an etch stopping layer,
wherein the silicon capping layer and etch stopping layer are sequentially disposed on the silicon germanium epitaxial layer.

16. The semiconductor device of claim 15 , further comprising:
a contact plug disposed on the silicon germanium epitaxial layer,
wherein the contact plug extends into the silicon capping layer, and
a metal silicide layer disposed between a bottom surface of the third epitaxial layer and the contact plug.

17. A semiconductor device comprising:
a semiconductor substrate;
a device isolating layer embedded within the semiconductor substrate and defining an active region;
a channel region formed in the active region;
a gate electrode disposed above the channel region;
a gate insulating layer provided between the channel region and the gate electrode; and
a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration and higher than the first concentration,
wherein the first epitaxial layer has a germanium concentration that increases with height and wherein the germanium concentration of the first epitaxial layer is within a range of 10 at % to 50 at %.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Nam Kyu
• Suh Dong Chan
• Lee Kwan Heum
• Lee Byeong Chan
• Lee Cho Eun
• Jung Su Jin
• Kim Gyeom
• Yoon Ji Eon

Classifications

• H01L29/7848 Primary

  Electricity · mapped topic

• H01L29/41766

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/7834

  Electricity · mapped topic