High speed interface protection apparatus

Patent metadata

Field	Value
Publication number	US-10008490-B2
Application number	US-201715614048-A
Country	US
Kind code	B2
Filing date	Jun 5, 2017
Priority date	Apr 7, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

The disclosed technology relates to electronics, and more particularly, to protection devices that protect circuits from transient electrical events such as electrical overstress/electrostatic discharge. A protection device includes a semiconductor substrate having formed therein at least two wells and a deep well underlying and contacting the at least two wells. The device additionally includes a first PN diode formed in one of the at least two wells and having a first heavily doped region of a first conductivity type and a first heavily doped region of a second conductivity type, and includes a second PN diode formed in one of the at least two wells and having a second heavily doped region of the first conductivity type and a second heavily doped region of the second conductivity type. The device additionally includes a first PN diode and the second PN diode are electrically shorted by an electrical shorting structure to form a first plurality of serially connected diodes having a threshold voltage. The device further includes a PNPN silicon-controlled rectifier (SCR) having a trigger voltage and comprising the first heavily doped region of the first conductivity type, the at least two wells, the deep well, and the second heavily doped region of the second conductivity type.

First claim

What is claimed is:

1. An integrated circuit apparatus comprising at least one integrated semiconductor device formed in a semiconductor substrate, the at least one integrated semiconductor device comprising:
a first well of a first conductivity type having formed therein a first PN diode comprising a first heavily doped region of a first conductivity type and a first heavily doped region of a second conductivity type, and further having formed at a surface a first floating metal layer between the first heavily doped region of the first conductivity type and the first heavily doped region of the second conductivity type;
a plurality of wells of a second conductivity type formed laterally adjacent to the first well of the first conductivity type, each well of the second conductivity type having a surface on which a floating metal layer is formed;
a plurality of wells of the first conductivity type formed laterally adjacent to the first well of the first conductivity type and alternating with the wells of the second conductivity type in a lateral direction, wherein each one of the plurality of wells of the first conductivity type has formed therein a diode comprising a heavily doped region of the first conductivity type, a heavily doped region of the second conductivity type and a floating metal layer formed at a surface between the respective heavily doped region of the first conductivity type and the respective heavily doped region of the second conductivity type.

2. The integrated circuit apparatus of claim 1 , wherein:
each of the plurality of wells of the first conductivity type alternates with an immediately adjacent well of the second conductivity type, the plurality of wells of the first conductivity type including a second well of the first conductivity type farthest from the first well of the first conductivity type, the second well of the first conductivity type including a second PN diode electrically shorted to the first PN diode by a first electrical shorting structure formed between the first heavily doped region of the second conductivity type and a second heavily doped region of the first conductivity type of the second well of the first conductivity type.

3. The integrated circuit apparatus of claim 2 , wherein a PNPN silicon-controlled rectifier (SCR) having a trigger voltage is formed by the first heavily doped region of the first conductivity type enclosed by the first well of the first conductivity type, the first well of the second conductivity type adjacent to the first well of the first conductivity type, a deep well of the second conductivity type, a third well of the first conductivity type adjacent to the first well of the second conductivity type, and a third heavily doped region of the second conductivity type formed in the third well of the first conductivity type.

4. The integrated circuit apparatus of claim 3 , further comprising:
a third PN diode formed in the third well of the first conductivity type and comprising a third heavily doped region of the first conductivity type and the third heavily doped region of the second conductivity type.

5. The integrated circuit apparatus of claim 4 , further comprising:
a fourth diode formed in a fourth well of the first conductivity type formed between the second and third wells of the first conductivity type, the fourth diode comprising a fourth heavily doped region of the first conductivity type and a fourth heavily doped region of the second conductivity type, wherein the second heavily doped region of the first conductivity type of the second well of the first conductivity type and the fourth heavily doped region of the fourth well of the first conductivity type are electrically shorted to each other by a second metallization structure.

6. The integrated circuit apparatus of claim 5 , wherein the heavily doped region of the first conductivity type of the fourth well of the first conductivity type and the second heavily doped region of the second conductivity type are electrically shorted to each other by a third metallization structure, such that serially connected diodes are formed, which includes the first PN diode and the second PN diode connected by the first metallization structure, the second PN diode and the fourth PN diode connected by the second metallization structure, and the fourth PN diode and the third PN diode connected by the third metallization structure.

7. The integrated circuit apparatus of claim 6 , wherein the second heavily doped region of the second conductivity type of the third well of the first conductivity type is connected to a first terminal, and wherein the first heavily doped region of the first conductivity type of the first well of the first conductivity type is connected to a second terminal, wherein the first terminal forms a common cathode of the PNPN SCR and the serially connected diodes, and wherein the second terminal forms a common anode of the PNPN SCR.

8. The integrated circuit apparatus of claim 1 comprising two integrated semiconductor devices of claim 1 arranged in an antiparallel configuration,
wherein one of the two semiconductor devices has an anode of the first PN diode connected to a first terminal and a cathode of a diode serially connected to the first PN diode formed in one of the plurality of wells of the first conductivity type connected to a second terminal, while the other of the two semiconductor devices has an anode of the first PN diode connected to the second terminal and a cathode of a diode formed in one of the plurality of wells of the first conductivity type connected to the first terminal, such that the two integrated semiconductor devices arranged in the antiparallel configuration is a bipolar protection device.

9. The integrated circuit apparatus of claim 8 , further comprising an Input/Output (IO), wherein the first terminal is configured such that current flows in a first direction from the first terminal to the IO in response to a voltage of a first polarity on the first terminal relative to the IO, and wherein the second terminal is configured such that current flows in a second direction opposite to the first direction from the second terminal to the IO in response to a voltage of a second polarity opposite to the first polarity relative to the IO.

10. An integrated circuit device, comprising:
a semiconductor substrate having formed therein a first bipolar junction transistor (BJT) and a second bipolar junction transistor (BJT) configured as a PNPN silicon-controlled rectifier (SCR) having a trigger voltage, the PNPN SCR having a cathode electrically connected to a first terminal and an anode electrically connected to a second terminal; and
a plurality of serially connected diodes having a threshold voltage formed in the semiconductor substrate,
wherein the serially connected diodes comprise a first diode and the second diode formed laterally on opposite sides of the first BJT and electrically shorted by a first electrical shorting structure formed above the semiconductor substrate.

11. The integrated circuit device of claim 10 , wherein an emitter of the second BJT serving as the anode of the PNPN SCR and a p-type region of the first diode is electrically connected to the second terminal, and wherein an emitter of the first BJT serving as the cathode of the PNPN SCR and an n-type region of the second diode is electrically connected to the first terminal.

12. The integrated circuit device of claim 10 , further comprising:
a first well of a first conductivity type having formed therein the first diode; and
a second well of the first conductivity type having formed therein the second diode,
wherein the first and second wells of t

Assignees

• Analog Devices Inc

Inventors

• Salcedo Javier Alejandro
• Pfeifer Jonathan

Classifications

• H01L27/0259 Primary

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L27/0262

  Electricity · mapped topic

• H10D89/713

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H10D89/10

  Integrated device layouts · CPC title