Tensile stress resistant multilayer ceramic capacitor

Patent metadata

Field	Value
Publication number	US-10008330-B2
Application number	US-201815862668-A
Country	US
Kind code	B2
Filing date	Jan 5, 2018
Priority date	Sep 30, 2014
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A multilayer ceramic capacitor is configured such that “a” is a distance in a height direction between an effective portion and a first principal surface; “b” is a distance in a length direction between a first end surface and the effective portion in the length direction; “c” is a thickness of the thickest portion of a first base layer provided over the first principal surface; “d” is a distance in the length direction between the thickest portion of the first base layer provided over the first end surface and a portion of the first base layer located over the first principal surface and closest to a second end surface; and “e” is a maximum thickness of a portion of the first base layer provided over the first end surface; and f: the height of the ceramic body, and 2≤(c·d+e·f/2)/(a·b)≤6 is satisfied.

First claim

What is claimed is:

1. A multilayer ceramic capacitor comprising:
a ceramic body including first and second principal surfaces extending in a length direction and a width direction, first and second side surfaces extending in the length direction and a height direction, and first and second end surfaces extending in the width direction and the height direction;
a first internal electrode extending in the length direction and the width direction, provided in the ceramic body, and exposed at the first end surface;
a second internal electrode extending in the length direction and the width direction, provided in the ceramic body, exposed at the second end surface, and the second internal electrode facing the first internal electrode in the height direction with a ceramic portion interposed therebetween;
a first external electrode connected to the first internal electrode and provided over the first end surface and over the first principal surface; and
a second external electrode connected to the second internal electrode and provided over the second end surface and over a portion of each of the first and second principal surfaces; wherein
the first external electrode includes a first base layer provided over a portion of the ceramic body and including a metal and glass, and a first plated layer provided over the first base layer;
the second external electrode includes a second base layer provided over a portion of the ceramic body and including a metal and glass, and a second plated layer provided over the second base layer;
the first and second plated layers each include a Cu plated layer; and
one of the following sets of conditions (a)-(e) is satisfied:
(a) the multilayer ceramic capacitor is about 0.9 mm or more and about 1.1 mm or less in length dimension, about 0.4 mm or more and about 0.6 mm or less in width dimension, and about 0.085 mm or more and about 0.11 mm or less in height dimension,
a maximum distance from the first principal surface to an internal electrode closest to the first principal surface among the first internal electrode and the second internal electrode in the height direction is referred to as T MAX ;
a minimum distance from the first principal surface to the internal electrode closest to the first principal surface in the height direction is referred to as T MIN ; and
a ratio (T MAX −T MIN )/T is about 1.0% to about 5.0%;

(b) the multilayer ceramic capacitor is about 0.9 mm or more and about 1.1 mm or less in length dimension, about 0.4 mm or more and about 0.6 mm or less in width dimension, and about 0.12 mm or more and about 0.15 mm or less in height dimension;
a maximum distance from the first principal surface to an internal electrode closest to the first principal surface among the first internal electrode and the second internal electrode in the height direction is referred to as T MAX ;
a minimum distance from the first principal surface to the internal electrode closest to the first principal surface in the height direction is referred to as T MIN ; and
a ratio (T MAX −T MIN )/T is about 1.3% to about 5.3%;

(c) the multilayer ceramic capacitor is about 0.9 mm or more and about 1.1 mm or less in length dimension, about 0.4 mm or more and about 0.6 mm or less in width dimension, and about 0.18 mm or more and about 0.20 mm or less in height dimension;
a maximum distance from the first principal surface to an internal electrode closest to the first principal surface among the first internal electrode and the second internal electrode in the height direction is referred to as T MAX ;
a minimum distance from the first principal surface to the internal electrode closest to the first principal surface in the height direction is referred to as T MIN ; and
a ratio (T MAX −T MIN )/T is about 1.5% to about 5.0%;

(d) the multilayer ceramic capacitor is about 0.9 mm or more and about 1.1 mm or less in length dimension, about 0.4 mm or more and about 0.6 mm or less in width dimension, and about 0.21 mm or more and about 0.23 mm or less in height dimension;
a maximum distance from the first principal surface to an internal electrode closest to the first principal surface among the first internal electrode and the second internal electrode in the height direction is referred to as T MAX ;
a minimum distance from the first principal surface to the internal electrode closest to the first principal surface in the height direction is referred to as T MIN ; and
a ratio (T MAX −T MIN )/T is about 1.8% to about 5.9%; and

(e) the multilayer ceramic capacitor is about 0.9 mm or more and about 1.1 mm or less in length dimension, about 0.4 mm or more and about 0.6 mm or less in width dimension, and about 0.024 mm or more and about 0.30 mm or less in height dimension;
a maximum distance from the first principal surface to an internal electrode closest to the first principal surface among the first internal electrode and the second internal electrode in the height direction is referred to as T MAX ;
a minimum distance from the first principal surface to the internal electrode closest to the first principal surface in the height direction is referred to as T MIN ; and
a ratio (T MAX −T MIN )/T is about 1.2% to about 6.0%.

2. The multilayer ceramic capacitor according to claim 1 , wherein
a height of an effective portion that is a portion of the ceramic body where the first and second internal electrodes overlap each other in the height direction is referred to as A in the height direction; and
a height of a first outer layer portion that is a portion of the ceramic body located between the first principal surface and the effective portion is referred to as B in the height direction; and
a height of a second outer layer portion that is a portion of the ceramic body located between the second principal surface and the effective portion is referred to as C in the height direction;
each of ratios A/B and A/C is within a range of about 0.5 to about 16.

3. The multilayer ceramic capacitor according to claim 1 , wherein a height dimension of the ceramic body is DT, a length dimension of the ceramic body is DL, and a width dimension of the ceramic body is DW, and a relationship ( 1/7)DW≤DT≤(¼)DW is satisfied.

4. The multilayer ceramic capacitor according to claim 1 , wherein a height dimension of the ceramic body is DT and a relationship DT<about 0.15 mm is satisfied.

5. The multilayer ceramic capacitor according to claim 1 , wherein the ceramic portion is about 0.5 μm to about 10 μm in height.

6. The multilayer ceramic capacitor according to claim 1 , wherein each of the first internal electrode and the second internal electrode is about 0.2 μm to about 2 μm in height.

7. The multilayer ceramic capacitor according to claim 1 , wherein each of the first and second base layers is about 1 μm to about 20 μm in thickness.

8. The multilayer ceramic capacitor according to claim 1 , wherein the Cu plated layer is about 1 μm to about 10 μm in thickness.

9. The multilayer ceramic capacitor according to claim 1 , wherein the Cu plated layer includes a plurality of plated films.

10. An electronic component comprising:
a multilayer printed wiring board; and
the multilayer ceramic capacitor according to claim 1 embedded in the multilayer printed wiring board.

11. The electronic component according to claim 10 , wherein a via hole is provided in the multilayer printed wiring board to provide electrical connection to the multilayer ceramic capacitor.

Assignees

• Murata Manufacturing Co

Inventors

• Itamura Hiroto

Classifications

• H01G2/065

  for surface mounting, e.g. chip capacitors · CPC title

• H05K1/182

  associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] · CPC title

• H01G4/1227

  based on alkaline earth titanates · CPC title

• H01G4/30

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/2325 Primary

  characterised by the material of the terminals · CPC title