Boltzmann machine circuit

Patent metadata

Field	Value
Publication number	US-10007877-B2
Application number	US-201615130377-A
Country	US
Kind code	B2
Filing date	Apr 15, 2016
Priority date	Jun 30, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A Boltzmann machine circuit includes: a plurality of circuits each circuit configured to add one or more first values based on one or more outputs of one or more circuits which are included in the plurality of circuits and are other than the circuit and convert an addition result into an analog signal, compare the analog signal with a second value, and output a comparison result; a plurality of arithmetic circuits configured to multiply the respective comparison results by respective weight values and generate the first values; and a control circuit configured to amplify an amplitude of the analog signal generated by each of the plurality of circuits.

First claim

What is claimed is:

1. A Boltzmann machine circuit comprising:
a plurality of circuits each circuit configured to add one or more first values based on one or more outputs of one or more circuits which are included in the plurality of circuits and are other than the circuit and convert an addition result into an analog signal, compare the analog signal with a second value, and output a comparison result;
a plurality of arithmetic circuits configured to multiply the respective comparison results by respective weight values and generate the first values; and
a control circuit configured to amplify an amplitude of the analog signal generated by each of the plurality of circuits,
wherein each of the plurality of circuits includes:
a digital addition circuit configured to add the first values corresponding to digital values;
a digital-analog converter configured to convert the addition result output from the digital addition circuit into the analog signal; and
a comparator configured to compare the analog signal output from the digital-analog converter with the second value.

2. The Boltzmann machine circuit according to claim 1 , wherein the control circuit equivalently performs annealing by amplifying the amplitude of the analog signal.

3. The Boltzmann machine circuit according to claim 1 , wherein the control circuit increases gain of the digital-analog converter to amplify the amplitude of the analog signal.

4. The Boltzmann machine circuit according to claim 1 , wherein each of the plurality of arithmetic circuits includes an AND circuit to which the comparison result and the weight value are input.

5. The Boltzmann machine circuit according to claim 1 , further comprising:
a learning circuit configured to calculate, based on the comparison results from the plurality of circuits, the weight value to be supplied to each of the plurality of arithmetic circuits.

6. The Boltzmann machine circuit according to claim 5 , wherein the learning circuit includes: an AND circuit configured to receive the comparison results from the plurality of circuits; a counter circuit configured to count an output of the AND circuit; and an encoder configured to output the weight values based on an output of the counter circuit.

Assignees

• Fujitsu Ltd

Inventors

• Chen Yanfei
• Tsukamoto Sanroku
• Tamura Hirotaka

Classifications

• G06N3/065 Primary

  Analogue means · CPC title

• G06N3/044

  Recurrent networks, e.g. Hopfield networks · CPC title

• G06N3/08 Primary

  Learning methods · CPC title