Technologies for control flow exploit mitigation using processor trace

Patent metadata

Field	Value
Publication number	US-10007784-B2
Application number	US-201514670988-A
Country	US
Kind code	B2
Filing date	Mar 27, 2015
Priority date	Mar 27, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

Technologies for control flow exploit mitigation include a computing device having a processor with real-time instruction tracing support. During execution of a process, the processor generates trace data indicative of control flow of the process. The computing device analyzes the trace data to identify suspected control flow exploits. The computing device may use heuristic algorithms to identify return-oriented programming exploits. The computing device may maintain a shadow stack based on the trace data. The computing device may identify indirect branches to unauthorized addresses based on the trace data to identify jump-oriented programming exploits. The computing device may check the trace data whenever the process is preempted. The processor may detect mispredicted return instructions in real time and invoke a software handler in the process space of the process to verify and maintain the shadow stack. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. A computing device for exploit mitigation, the computing device comprising:
a hardware processor comprising a processor trace module to generate trace data indicative of control flow of a process of the computing device during an execution of the process, wherein the control flow comprises an order of instructions executed by the processor;
an exploit detector module to:
(i) detect preemption of the process during the execution of the process;
(ii) in response to detection of the preemption of the process, analyze the trace data using a heuristic algorithm to identify a suspected control flow exploit that is a suspected return-oriented programming exploit, wherein to analyze the trace data using the heuristic algorithm to identify the suspected return-oriented programming exploit comprises to:
identify a first target instruction pointer packet in the trace data, wherein the first target instruction pointer packet is associated with a destination address;
find a return instruction in memory at an address that follows the destination address of the first target instruction packet; and
identify the suspected return-oriented programming exploit in response to finding the return instruction in memory; and

(iii) determine a cost value in response to identification of the suspected control flow exploit, wherein the cost value is indicative of a likelihood that the suspected control flow exploit is an actual control flow exploit, wherein to determine the cost value comprises to:
(a) subtract the cost value from a total cost budget, wherein the total cost budget is associated with the process; and
(b) determine whether the total cost budget has been exceeded; and

a security response module to handle the suspected control flow exploit in response to a determination that the total cost budget has been exceeded.

2. The computing device of claim 1 , wherein to analyze the trace data using the heuristic algorithm to identify the suspected return-oriented programming exploit further comprises to:
identify a pair of successive target instruction pointer packets in the trace data, wherein the pair of successive target instruction pointer packets includes the first target instruction pointer packet;
wherein to identify the suspected return-oriented programming exploit further comprises to identify the suspected return-oriented programming exploit in response to identification of the pair of successive target instruction pointer packets.

3. The computing device of claim 1 , wherein to analyze the trace data using the heuristic algorithm to identify the suspected return-oriented programming exploit further comprises to:
determine whether the first target instruction pointer packet is preceded by a flow update packet in the trace data;
wherein to identify the suspected return-oriented programming exploit further comprises to identify the suspected return-oriented programming exploit in response to a determination that the first target instruction pointer packet is not preceded by a flow update packet in the trace data.

4. The computing device of claim 1 , wherein:
the exploit detector module is further to (i) identify a non-suspicious instruction based on the trace data, wherein to identify the non-suspicious construction comprises to identify a taken/not-taken packet in the trace data; and (ii) reset the total cost budget in response to identification of the non-suspicious instruction.

5. The computing device of claim 1 , wherein:
to generate the trace data indicative of the control flow of the process of the computing device comprises to output a target instruction pointer packet including a next linear instruction pointer in response to execution of a direct call instruction; and
to analyze the trace data to identify the suspected control flow exploit further comprises to (i) update a shadow stack based on the trace data and (ii) analyze the shadow stack using a heuristic algorithm to identify a suspected return-oriented programming exploit.

6. The computing device of claim 5 , wherein to generate the trace data indicative of the control flow of the process of the computing device further comprises to:
output a packet including a current stack pointer value in response to execution of a call instruction or a return instruction.

7. The computing device of claim 1 , wherein to analyze the trace data to identify the suspected control flow exploit further comprises to:
identify a first target instruction pointer packet in the trace data, wherein the first target instruction pointer packet is associated with a destination address;
determine whether the destination address is a predefined legitimate branch target; and
identify a suspected jump-oriented programming exploit in response to a determination that the destination address is not a predefined legitimate branch target.

8. A computing device for real-time exploit mitigation, the computing device comprising:
a hardware processor comprising a processor trace module to:
generate trace data indicative of control flow of a process of the computing device during an execution of the process, wherein the control flow comprises an order of instructions executed by the processor;
detect a suspected control flow exploit using a heuristic algorithm to identify a suspected return-oriented programming exploit that is a mispredicted return instruction using the trace data; and
in response to detection of the suspected control flow exploit, invoke a suspected control flow exploit handler wherein the suspected control flow exploit handler comprises a mispredicted return handler;

an exploit detector module to in response to invocation of the suspected control flow exploit handler, determine whether a current shadow stack is valid, and update the current shadow stack based on the trace data in response to a determination that the current shadow stack is valid; and
a security response module to handle the suspected control flow exploit in response to a determination that the current shadow stack is not valid.

9. The computing device of claim 8 , wherein the exploit detector module is further to:
compute a message authentication code based on the current shadow stack in response to updating of the current shadow stack;
encode the message authentication code using a handler key, wherein the handler key is located in a protected memory region; and
output the encoded message authentication code to the trace data.

10. The computing device of claim 9 , wherein to output the encoded message authentication code comprises to execute a processor instruction to write the encoded message authentication code to the trace data.

11. The computing device of claim 9 , wherein to output the encoded message authentication code comprises to execute one or more branch instructions based on the encoded message authentication code to output coded data to the trace data.

12. The computing device of claim 8 , wherein to determine whether the current shadow stack is valid comprises to:
extract an encoded first message authentication code from the trace data, wherein the encoded first message authentication code was previously output to the trace data;
compute a second message authentication code based on the current shadow stack;
encode the second message authentication code to generate an encoded second message authentication code using a handler key, wherein the handler key is located in a protected memory region; and
compare the encoded first message authentication code to the encoded second message authentication code.

13. The computing device of claim 12 , wherein to encode the second

Assignees

• Intel Corp

Inventors

• Lemay Michael
• Sahita Ravi L
• Strong Beeman C
• Schmitt Thilo
• Bulygin Yuriy
• Metzger Markus T

Classifications

• G06F21/44

  Program or device authentication · CPC title

• G06F21/56 Primary

  Computer malware detection or handling, e.g. anti-virus arrangements · CPC title

• G06F21/52 Primary

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title