Method to enable intel mini-mezz open compute project (OCP) plug-and-play network phy cards

Patent metadata

Field	Value
Publication number	US-10007634-B2
Application number	US-201514961010-A
Country	US
Kind code	B2
Filing date	Dec 7, 2015
Priority date	Dec 7, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

Methods for implementing mini-mezzanine Open Compute Project (OCP) plug-and-play Network PHY Cards and associated apparatus. In accordance with one aspect, the MAC (Media Access Channel) and PHY (Physical) layer functions in one or more communication protocol stacks are split between a MAC block in a Platform Controller Hub (PCH) or processor SoC and a PHY card installed in a mezzanine slot of a platform and including one or more ports. During platform initialization operations, configuration parameters are read from the PHY card including a PHY card ID, and a corresponding configuration script is selected and executed to configure the PHY card for use in the platform. The configuration parameters are also used to enumerate PCIe devices associated with physical functions and ports supported by the PHY card.

First claim

What is claimed is:

1. An integrated circuit (IC), configured to be installed in a computer platform including a Physical layer (PHY) card, comprising:
a media access control (MAC) block, configured to implement MAC layer functionality associated with one or more communication protocol stacks that include a Physical layer;
an interface, configured to couple signals between the MAC block and the PHY card when the IC is installed in the computer platform, the PHY card including at least one port and configured to support Physical layer functionality associated with at least one communication protocol stack among the one or more communication protocol stacks; and
firmware instructions, stored on the IC, configured to be executed by one of a processing element on the IC or on a processing element in a processor to which the IC is configured to be coupled to when installed in the computer platform, the firmware instructions coded, upon execution, to configure the PHY card for use in the computer platform.

2. The IC of claim 1 , wherein the IC comprises a Platform Controller Hub (PCH) configured to interface to a processor.

3. The IC of claim 1 , wherein the IC comprises a processor System on a Chip (SoC).

4. The IC of claim 1 , wherein the compute platform includes a mezzanine card slot configured in accordance with an Open Computer Platform (OCP) specification, and the PHY card comprises a mezzanine PHY card configured to be installed the mezzanine card slot.

5. The IC of claim 1 , wherein the interface comprises a MAC-to-PHY interface configured to interface with a PHY interface on the PHY card.

6. The IC of claim 1 , wherein the interface comprises a MAC interface configured to interface with a MAC-to-PHY interface on the PHY card.

7. The IC of claim 1 , wherein the IC further includes non-volatile memory, and wherein the firmware instructions, when executed, are configured to cause the IC to:
read PHY card configuration data stored on the PHY card including a PHY card identifier (ID); and
compare the PHY card ID to a list of valid PHY card IDs stored in the non-volatile memory to determine whether the PHY card is supported by the IC.

8. The IC of claim 1 , wherein the firmware instructions, when executed, are configured to cause the IC to:
read configuration parameters from the PHY card, including a number of ports provided by the PHY card, and at least one of a device and subdevice ID for each port; and
program Peripheral Component Interconnect Express (PCIe) configuration parameters corresponding to the configuration parameters that are read into a PCIe configuration space associated with the MAC block.

9. The IC of claim 8 , wherein the firmware instructions, when executed, are configured to cause the IC to:
store, on the IC, a current PHY card identifier (ID) corresponding to a PHY card currently installed in the computer platform;
during a subsequent initialization of the computer platform,
read a PHY card identifier (ID) stored on a PHY card installed in the compute platform during the subsequent initialization of the computer platform; and
compare the PHY card ID that is read to the current PHY card ID that is stored, and if there is a match, use the PCI configuration parameters programmed into the PCIe configuration space.

10. The IC of claim 8 , wherein the IC further comprises a PCIe Root Complex and a PCIe interconnect segment to which the MAC block is coupled, and wherein the IC is configured, when operating, to read the PCIe configuration parameters and enumerate one or more PCIe devices corresponding to Physical functions supported by the PHY card.

11. The IC of claim 1 , wherein a PHY configuration script for each of at least one PHY card is stored on the IC, and wherein the firmware instructions, when executed, are configured to cause the IC to:
read a PHY card identifier (ID) stored on the PHY card;
select a PHY configuration script stored on the IC based on the PHY card ID; and
execute the PHY configuration script to configure the PHY card.

12. A method, comprising:
reading PHY card configuration data stored on a PHY card including a PHY card identifier (ID), the PHY card installed in a computer platform including at least one port and configured to support Physical layer functionality associated with at least one communication protocol stacks and to communicate with a Media Access Control (MAC) block configured to support MAC layer functionality for the at least one communication protocol stack, the MAC block implemented in an integrated circuit (IC) component in the computer platform that is separate from the PHY card;
comparing the PHY card ID to a list of valid PHY card IDs to determine whether the PHY card is a valid PHY card; and
if the PHY card is determined to be a valid PHY card, configuring the PHY card to implement Physical layer functionality associated with the at least one communication protocol stack for at least one port.

13. The method of claim 12 , further comprising:
reading configuration parameters from the PHY card, including a number of ports provided by the PHY card, and at least one of a device and subdevice ID for each port; and
programming Peripheral Component Interconnect Express (PCIe) configuration parameters corresponding to the configuration parameters that are read into a PCIe configuration space associated with the MAC block.

14. The method of claim 12 , further comprising reading the PCIe configuration parameters and enumerating one or more PCIe devices corresponding to Physical functions supported by the PHY card.

15. The method of claim 12 , further comprising:
storing a current PHY card identifier (ID) corresponding to a PHY card installed in the computer platform on the IC component;
during a subsequent initialization of the compute platform,
reading a PHY card identifier (ID) stored on the PHY card;
comparing the PHY card ID that is read to the current PHY card ID that is stored, and if there is a match, use the PCIe configuration parameters programmed into the PCIe configuration space.

16. The method of claim 12 , further comprising:
storing a PHY configuration script for at least one PHY card;
selecting a PHY configuration script based on the PHY card ID that is read; and
executing the PHY configuration script to configure the PHY card.

17. The method of claim 12 , further comprising:
determining the PHY card ID corresponds to a PHY card that is not supported by the MAC layer block;
writing out an error code; and
propagating the error code to a Peripheral Component Interconnect Express (PCIe) configuration space associated with the MAC block.

18. The method of claim 12 , further comprising implementing communication between the IC component and the PHY card using at least one sideband channel.

19. The method of claim 12 , wherein the PHY card is installed in a mezzanine card slot configured in accordance with an Open Computer Platform (OCP) mezzanine card specification.

20. A computer platform comprising:
a main board;
a mezzanine card slot including a connector communicatively coupled to the main board;
a PHY card, coupled to the connector and installed in the mezzanine card slot, the PHY card including at least one port and configured to support Physical (PHY) layer functionality associated with at least one communication protocol stack including a media access control (MAC) layer; and
an integrated circuit (IC) chip, mounted on the main board and including,
a MAC block, configured to implement MAC layer funct

Assignees

• Dubal Scott P
• Louzoun Eliel
• Boom Douglas
• Lusted Kent C
• Barbee Ronald F
• Shah Nishantkumar
• Intel Corp

Inventors

• Dubal Scott P
• Louzoun Eliel
• Boom Douglas
• Lusted Kent C
• Barbee Ronald F
• Shah Nishantkumar

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/36

  for access to common bus or bus system · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/4081

  Live connection to bus, e.g. hot-plugging (current or voltage limitation during live insertion H02H9/004) · CPC title

• G06F13/42 Primary

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title