Method and apparatus for automatic signal exchange between multiple embedded CPU boards

Patent metadata

Field	Value
Publication number	US-10007627-B2
Application number	US-201415039254-A
Country	US
Kind code	B2
Filing date	Nov 12, 2014
Priority date	Dec 19, 2013
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A signal name based method for automatic signal exchange between multiple embedded CPU boards, includes: dividing CPU boards into master board and slave board, where each slave board sends signal registration information to the master board; reading an exchange relationship between an output signal and an input signal that is represented by a connection line between signal names, calculating and allocating a data bus address to which the output signal and the input signal are mapped, and sending memory addresses, data types, and bus addresses of signals to each slave board; saving these as output signal tables and input signal tables; and writing, by a signal sender, a value of an output signal into a corresponding bus address according to the output signal tables, and reading, by a receiver, a value of an input signal from a corresponding bus address according to the input signal tables.

First claim

What is claimed:

1. A method for automatic signal exchange between multiple embedded CPU boards, comprising the following steps:
(1) dividing CPU boards in a distributed system of multiple embedded CPU boards into master board and slave board, wherein a CPU board with a signal management function is used as the master board, and the remaining CPU boards are used as slave boards; and during an initialization phase, each slave board sends signal registration information to the master board;
(2) after the master board collects the signal registration information of all the slave boards, reading, from a configuration file, an exchange relationship between an output signal and an input signal that is represented by a connection line between signal names, calculating and allocating a data bus address to which the output signal and the input signal are mapped, and sending memory addresses, data types, and bus addresses of signals to each slave board;
(3) after a slave board receives the memory addresses, the data types, and the bus addresses of the signals from the master board, saving same as output signal tables and input signal tables; and
(4) during an operation phase, writing, by a signal sender, a value of an output signal into a corresponding allocated bus address according to the output signal tables, and reading, by a receiver, a value of an input signal from a corresponding bus address according to the input signal tables.

2. The method for automatic signal exchange between multiple embedded CPU boards according to claim 1 , wherein in step (1), each slave board sends signal registration information to the master board by using CAN, RS-485, or Ethernet, and the signal registration information comprises a signal name, a signal memory address, and a signal data type.

3. The method for automatic signal exchange between multiple embedded CPU boards according to claim 1 , wherein in step (1), during an initialization phase, the master board sends a registration start command to each slave board, and a slave board that receives a registration start command sends signal registration information to the master board.

4. The method for automatic signal exchange between multiple embedded CPU boards according to claim 1 , wherein in step (2), after acquiring the signal registration information of all the slave boards, the master board stores the signal registration information as an output signal registration table and an input signal registration table according to an output type and an input type; storage of the registration tables is performed by using arrays; each array item represents information about one signal, comprising a signal name string, a number of a board to which the signal belongs, a signal data type, and a signal memory address; and after all the signals are registered, a signal information table is ordered according to signal names.

5. The method for automatic signal exchange between multiple embedded CPU boards according to claim 4 , wherein in step (2), the master board reads, from a configuration file, an exchange relationship between an output signal and an input signal that is represented by a connection line between signal names, which comprises the following specific content: the master board reads a configuration file, extracts connection lines between signal names one by one, and stores the connection lines as an array of a signal exchange relationship table, wherein each array item represents one signal connection line; and the master board obtains, by searching, information about signals from the output signal registration table according to output signal names in the signal exchange relationship table, and then reorders items in the signal exchange relationship table according to a board address, a data type, and a memory address order of the output signals, wherein a specific ordering rule is that: signals with different board numbers are ordered according to the board numbers in ascending order, signals of a same board are ordered according to widths of signal data types in ascending order, and signals of a same board and a same data type are ordered according to memory addresses in ascending order.

6. The method for automatic signal exchange between multiple embedded CPU boards according to claim 5 , wherein an order of the widths of data types in ascending order is: Boolean, single-byte integer, double-byte integer, four-byte integer, and floating-point.

7. An apparatus for automatic signal exchange, comprising: a registration module, an allocation module, a storage module, and an execution module, wherein
the registration module is configured to enable each slave board to send signal registration information to the master board;
the allocation module is configured to enable the master board to parse a configuration file, to calculate and allocate a data bus address to which an output signal and an input signal are mapped, and to sequentially send memory addresses, data types, and bus addresses of signals to each slave board;
the storage module is configured to enable a slave board to save, after the slave board receives the memory addresses, the data types, and the bus addresses of the signals from the master board, same as output signal tables and input signal tables; and
the execution module is configured to, enable a signal sender to write, during an operation phase, a value of an output signal into a corresponding allocated bus address according to the output signal tables, and enable a receiver to read a value of an input signal from a corresponding bus address according to the input signal tables.

8. The apparatus according to claim 7 , wherein the apparatus further comprises: the registration module, wherein
the registration module is configured to, enable each slave board to send signal registration information to the master board by using CAN, RS-485, or Ethernet, wherein the signal registration information comprises a signal name, a signal memory address, and a signal data type, enable, during an initialization phase, the master board to send a registration start command to each slave board, and enable a slave board that receives a registration start command to send signal registration information to the master board.

9. The apparatus according to claim 7 , wherein the apparatus further comprises: the allocation module, wherein
the allocation module is configured to, enable the master board to store, after acquiring the signal registration information of all the slave boards, the signal registration information as an output signal registration table and an input signal registration table according to an output type and an input type, wherein storage of the registration tables is performed by using arrays; each array item represents information about one signal, comprising a signal name string, a number of a board to which the signal belongs, a signal data type, and a signal memory address; and after all the signals are registered, a signal information table is ordered according to signal names.

10. The apparatus according to claim 7 , wherein the allocation module is specifically configured to, enable the master board to read, from a configuration file, an exchange relationship between an output signal and an input signal that is represented by a connection line between signal names, which comprises the following specific content: the master board reads a configuration file, extracts connection lines between signal names one by one, and stores the connection lines as an array of a signal exchange relationship table, wherein each array item represents one signal connection line; and enable the master board to obtain, by searching, information about signals from the output signal registratio

Assignees

• Nr Electric Co Ltd
• Nr Electric Eng Co Ltd

Inventors

• Feng Yadong
• Zhou Qiang
• Xu Dongfang
• Yuan Tao
• Zhao Tianen
• Li Guanghua
• Wen Jifeng
• Chen Hongjun
• Liu Kejin

Classifications

• G05B19/41845 Primary

  characterised by system universality, reconfigurability, modularity · CPC title

• G06F15/17

  using an input/output type connection, e.g. channel, I/O port · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F30/00

  Computer-aided design [CAD] · CPC title

• G06F13/362 Primary

  with centralised access control · CPC title