Secured pseudo-random number generator

Patent metadata

Field	Value
Publication number	US-10007488-B2
Application number	US-201715813286-A
Country	US
Kind code	B2
Filing date	Nov 15, 2017
Priority date	Oct 10, 2016
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

The present invention provides a method of generating a sequence of pseudo-random numbers which are difficult to predict. The method includes: (i) generating a plurality of candidate pseudo-random numbers by a respectively corresponding plurality of (differently structured) linear feedback shift registers; (ii) generating a “selector number” from one or more additional linear feedback shift registers; and (iii) selecting a candidate number from the plurality of candidate numbers, based on the “selection number” to produce a selected pseudo-random number for output.

First claim

What is claimed is:

1. A method comprising:
receiving, by a selector, a plurality of pseudo-random numbers (PRNs) including a first pseudo-random number (PRN), a second PRN, and a third PRN;
selecting, from the plurality of PRNs, a selected PRN, based at least in part upon the first PRN; and
outputting the selected PRN;
wherein:
the plurality of PRNs are generated by a corresponding plurality of pseudorandom number generators (PRNGs) respectively including a first PRNG, a second PRNG, and a third PRNG,
feedback configurations of the first PRNG, the second PRNG and the third PRNG are mutually unique,
the second PRNG is a Fibonacci linear feedback shift register (LFSR),
the third PRNG is a Galois LFSR,
a full PRN generated by a PRNG of the plurality of PRNGs, the full PRN having a length of n bits, is partitioned into two or more PRNs having respective lengths of less than n bits, and
a PRNG of the plurality of PRNGs is provided with a different seed each time a random number is generated by the PRNG.

Assignees

• IBM

Inventors

• Kawai Yutaka
• Miwa Yohichi

Classifications

• G06F7/582 Primary

  Pseudo-random number generators · CPC title

• G06F7/584 Primary

  using finite field arithmetic, e.g. using a linear feedback shift register · CPC title