Power saving in multi-directional data transfer

Patent metadata

Field	Value
Publication number	US-10007319-B2
Application number	US-201514972246-A
Country	US
Kind code	B2
Filing date	Dec 17, 2015
Priority date	Dec 17, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A power-saving method and circuit in a data processing device comprising a data buffer. Data transfer commands associated with a data source and a data destination are received at the data processing device. The data transfer commands are accumulated until an amount of data associated with the read commands is greater than a predefined threshold. When the amount of data is less than the predefined threshold and the data buffer is empty, the data buffer is signaled to enter or to maintain a power saving mode. When the amount of data is at least the predefined threshold, the data buffer is signaled to exit the power saving mode following a predetermined delay. Processing of the commands and data in respective pipelines is monitored to time exiting of the buffer from the power saving mode for arrival of the data. Power saving mode use and thus power saving are optimized.

First claim

The invention claimed is:

1. A power-saving method in a data processing device comprising a data buffer, the method comprising:
receiving at the data processing device data transfer commands associated with a data source and a data destination, the data source and the data destination being associated with the data buffer of the data processing device;
accumulating the data transfer commands at the data processing device until an amount of data associated with the data transfer commands is greater than a predefined threshold;
when the amount of data is less than the predefined threshold and the data buffer is empty, signaling the data buffer to enter or to maintain a power saving mode; and
when the amount of data is at least the predefined threshold, signaling the data buffer to exit the power saving mode following a predetermined delay.

2. The power-saving method according to claim 1 , wherein, when the amount of data is at least the predefined threshold and the data buffer is empty, the method further comprises: determining a data processing time of the data; and delaying the signaling of the data buffer to exit the power saving mode and determining the delay based on the data processing time.

3. The power-saving method according to claim 2 , wherein determining the delay based on the data processing time comprises:
comparing the data processing time to a power saving mode exit time of the power saving mode;
if the power saving mode exit time is less than the data processing time:
waiting until a remaining data processing time equals the power saving mode exit time plus a first preconfigured further time;

if the power saving mode exit time is not less than the data processing time:
waiting until a sum of:
a remaining command processing time of the data transfer commands;
a data transfer time of the data from the data source; and
the data processing time,

equals the power saving mode exit time plus a second preconfigured further time.

4. The power-saving method according to claim 3 , wherein the first preconfigured further time and the second preconfigured further time each equals zero.

5. The power-saving method according to claim 3 , wherein the first preconfigured further time and the second preconfigured further time each equals a preconfigured number of clock cycles.

6. The power-saving method according to claim 3 , wherein the determining of the data processing time of the data comprises is based on a number of stages of a data register pipeline.

7. The power-saving method according to claim 6 , wherein waiting until the remaining data processing time equals the power saving mode exit time comprises waiting until the data reaches one of the stages of the data register pipeline such that the remaining data processing time equals the power saving mode exit time.

8. The power-saving method according to claim 3 , wherein the remaining command processing time of the data transfer commands is based on a remaining number of stages of a command register pipeline.

9. The power-saving method according to claim 8 , wherein waiting until the sum is equal to the power saving mode exit time comprises waiting until the data transfer commands reach one of the stages of the command register pipeline such that the sum equals the power saving mode exit time.

10. The power-saving method according to claim 1 , further comprising, when the amount of data is at least the predefined threshold, launching generation of at least one data transfer request for the data from the data source.

11. The power-saving method according to claim 10 , wherein launching the at least one data transfer request comprises processing the data transfer commands in a command register pipeline to generate processed data transfer commands, generating the at least one data transfer request based on the processed data transfer commands, and transmitting the at least one data transfer request to a source port of the data processing device, the source port being associated with the data source.

12. The power-saving method according to claim 1 , wherein the data transfer commands comprise read commands.

13. A data transfer circuit comprising:
a command processing unit to receive data transfer commands and to accumulate the data transfer commands until an amount of data associated with the data transfer commands is greater than a predefined threshold;
a source port connected to receive at least one data transfer request based on the data transfer commands, the source port interfacing a data source to receive data based on the at least one data transfer request;
a data processing unit connected to the source port to receive the data and to process the data to generate processed data;
a data buffer connected to the data processing unit to buffer the processed data;
a destination port connected to the data buffer and interfacing the data destination to transmit the processed data from the data buffer to the data destination; and
a low-power controller logic connected to the command processing unit, the data processing unit, and the data buffer:
when the amount of data is less than the predefined threshold and the data buffer is empty, to signal the data buffer to enter or to maintain a power saying mode; and
when the amount of data is at least the predefined threshold, to signal the data buffer to exit the power saving mode following a predetermined delay.

14. The data transfer circuit according to claim 13 , wherein the low-power controller logic is further configured, when the amount of data is at least the predefined threshold and the data buffer is empty: to determine a data processing time of the data by the data processing unit; and to delay the signaling of the data buffer to exit the power saving mode and to determine the delay based on the data processing time.

15. The data transfer circuit according to claim 14 , wherein the low-power controller logic determines the delay based on the data processing time by:
comparing the data processing time to a power saving mode exit time of the power saving mode;
if the power saving mode exit time is less than the data processing time:
waiting until a remaining data processing time equals the power saving mode exit time plus a first preconfigured further time;

if the power saving mode exit time is not less than the data processing time:
waiting until a sum of:
a remaining command processing time of the data transfer commands;
a data transfer time of the data from the data source; and
the data processing time,

equals the power saving mode exit time plus a second preconfigured further time.

16. The data transfer circuit according to claim 15 , wherein the first preconfigured further time and the second preconfigured further time each equals zero.

17. The data transfer circuit according to claim 15 , wherein the first preconfigured further time and the second preconfigured further time each equals a preconfigured number of clock cycles.

18. The data transfer circuit according to claim 15 , wherein the data processing unit comprises a data register pipeline comprising a number of stages, and the low-power controller logic determines the data processing time of the data based on the number of stages of the data register pipeline.

19. The data transfer circuit according to claim 18 , wherein waiting until the remaining data processing time equals the power saving mode exit time comprises waiting until the data reaches one of the stages of the data register pipeline such that the remaining data processin

Assignees

• Pmc Sierra Us Inc
• Microsemi Solutions U S Inc

Inventors

• Kumar Amrendra
• Prasad Janardan
• Clinton David Joseph

Classifications

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• Y02D10/13

  Cross-Sectional Technologies · mapped topic

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic