Circuits and methods providing calibration for temperature mitigation in a computing device

Patent metadata

Field	Value
Publication number	US-10007310-B2
Application number	US-201615205678-A
Country	US
Kind code	B2
Filing date	Jul 8, 2016
Priority date	Jul 8, 2016
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A method includes generating temperature information from a plurality of temperature sensors within a computing device; and processing the temperature information to generate voltage reduction steps based on an observed rate of change of the temperature information.

First claim

What is claimed is:

1. A method comprising:
generating temperature information from a plurality of temperature sensors within a computing device;
storing a plurality of voltage reduction step values, each voltage reduction step value being associated with a frequency reduction step value and a temperature information rate of change value; and
processing the temperature information to generate voltage reduction steps based on an observed rate of change of the temperature information, wherein processing the temperature information comprises:
matching the observed rate of change of the temperature information to a particular stored temperature information rate of change value;
selecting a stored first voltage reduction step value corresponding to the particular stored temperature information rate of change value; and
reducing an operating voltage of the computing device by the stored first voltage reduction step value.

2. The method of claim 1 , further comprising:
lowering a performance of the computing device during normal operation of the computing device, and in response to further temperature information received during normal operation of the computing device.

3. The method of claim 2 , wherein lowering the performance of the computing device comprises reducing a frequency of operation of the computing device in addition to reducing a voltage of operation of the computing device.

4. The method of claim 2 , wherein lowering the performance of the computing device comprises reducing an operating voltage of the computing device according to voltage reduction steps in a temperature mitigation algorithm.

5. The method of claim 1 , wherein the voltage reduction steps are associated with respective frequency reduction steps.

6. The method of claim 1 , wherein the observed rate of change of the temperature information comprises:
a rate of change of temperature information associated with a junction temperature of the computing device.

7. The method of claim 6 , wherein the junction temperature of the computing device comprises a reading of a first temperature sensor of a plurality of temperature sensors of the device, wherein the reading is a highest reading of the plurality of temperature sensors.

8. The method of claim 1 , wherein:
the plurality of voltage reduction step values are stored as voltage deltas in the data structure; and
the associated frequency reduction step values and associated temperature information rate of change values are stored in the data structure.

9. The method of claim 8 , wherein the data structure comprises a look-up table.

10. The method of claim 8 , wherein matching the observed rate of change of the temperature information comprises:
parsing the data structure to match the observed rate of change of the temperature information to the particular stored temperature information rate of change value in the data structure.

11. The method of claim 10 , further comprising:
using the first voltage reduction step value during normal operation of the computing device.

12. A system comprising:
a computer processor configured to execute computer-readable instructions, the computer processor being installed in a computing device; and
a plurality of temperature sensors disposed within the computing device, the plurality of temperature sensors configured to communicate with the computer processor, the computer processor configured to perform the following operation:
gathering temperature data from the plurality of temperature sensors internal to a housing of the computing device during a first period of time;
measuring a temperature ramp rate of the computing device from the temperature data;
using the temperature ramp rate as a key to select a value from a data structure, wherein the value includes a voltage step size; and
reducing an operating voltage of the computing device by the voltage step size.

13. The system of claim 12 , wherein the plurality of temperature sensors are disposed on a printed circuit board of the computing device, and wherein the printed circuit board is enclosed within a housing of the computing device.

14. The system of claim 12 , wherein the plurality of temperature sensors are enclosed within a housing of the computing device.

15. The system of claim 12 , wherein the temperature ramp rate comprises a rate of change of a junction temperature during a calibration operation of the computing device.

16. The system of claim 12 , wherein the computer processor is further configured to reduce an operating voltage of the computer processor according to the voltage step size during normal operation.

17. A computing device comprising:
means for sensing temperature at a plurality of locations within an external housing of the computing device;
means for calculating a junction temperature ramp rate from temperature data from the temperature sensing means;
means for parsing a look-up table to select a voltage reduction step size value based on the junction temperature ramp rate; and
means for reducing an operating voltage by the voltage reduction step size value.

18. The computing device of claim 17 , wherein the means for calculating the junction temperature ramp rate comprises:
a plurality of temperature sensors, wherein a first subset of the plurality of temperature sensors are disposed within a semiconductor chip of the computing device, and wherein a second subset of the plurality of temperature sensors are disposed on a printed circuit board of the computing device.

19. The computing device of claim 17 , further comprising:
means for storing the voltage reduction step size value in a non-volatile memory of the computing device.

20. The computing device of claim 19 , further comprising:
means for retrieving the voltage reduction step size value from the non-volatile memory.

21. The computing device of claim 17 , wherein the means for calculating the junction temperature ramp rate comprises:
means for polling the temperature sensing means to determine a highest temperature reading among the temperature sensing means; and
means for generating the junction temperature ramp rate from the highest temperature reading among the temperature sensing means.

22. A method comprising:
gathering temperature data from a plurality of temperature sensors internal to a housing of a computing device during a first period of time;
measuring a temperature ramp rate of the computing device from the temperature data;
using the temperature ramp rate as a key to select a value from a data structure, wherein the value includes a voltage step size; and
reducing an operating voltage of the computing device by the voltage step size.

23. The method of claim 22 , wherein gathering temperature data further comprises:
calculating a junction temperature as a highest temperature reading value of the plurality of temperature sensors as temperature data is gathered; and
wherein measuring the temperature ramp rate comprises measuring a ramp rate of the junction temperature.

24. The method of claim 22 , wherein measuring the temperature ramp rate comprises:
calculating a skin temperature of the computing device; and
calculating a ramp rate of the skin temperature of the computing device.

25. The method of claim 22 , wherein the voltage step size comprises a voltage delta.

26. The method of claim 22 , wherein applying the voltage step size compr

Assignees

• Qualcomm Inc

Inventors

• Saeidi Mehdi
• Roshandell Melika
• Mittal Rajat

Classifications

• G06F1/203 Primary

  for portable computers, e.g. for laptops · CPC title

• G01R31/00

  Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere ({measuring superconductive properties G01R33/1238;} testing line transmission systems H04B3/46; testing or measuring semiconductors or solid state devices during manufacture {H10P74/00}) · CPC title

• G06F1/206 Primary

  comprising thermal management · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title