Board, integrated circuit testing arrangement, and method for operating an integrated circuit

Patent metadata

Field	Value
Publication number	US-10006942-B2
Application number	US-201313892398-A
Country	US
Kind code	B2
Filing date	May 13, 2013
Priority date	May 13, 2013
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A board may include a first set of board contact pads arranged on a first side of the board, the pads configured to connect to circuit pads of a circuit under test, the positions of the pads matching to the positions of the circuit pads; a fan-out region on the first side of the board including fan-out contact pads configured to at least one of receive a test signal and provide a measurement signal; at least one contact pad connecting to at least one pad of the first set of board pads; and a second set of board contact pads on a second side of the board, the second set of board pads configured to connect to test board pads of a test board; positions of the pads matching to the positions of the test board pads; a pad connecting to a pad of the first set of board pads.

First claim

What is claimed is:

1. A board, comprising:
a first set of board contact pads arranged on a first side of the board, the contact pads of the first set of board contact pads configured to electrically conductively connect to integrated circuit contact pads of an integrated circuit under test, the positions of the contact pads of the first set of board contact pads matching to the positions of the integrated circuit contact pads;
a fan-out region in the first side of the board, the fan-out region comprising one or more fan-out contact pads configured to at least one of receive a test signal and provide a measurement signal; at least one contact pad of the one or more fan-out contact pads electrically conductively connecting to at least one contact pad of the first set of board contact pads; and
a second set of board contact pads on a second side of the board, the second set of board contact pads being configured to electrically conductively connect to test board contact pads of a test board; the positions of the contact pads of the second set of board contact pads matching to the positions of the test board contact pads; at least one contact pad of the second set of board contact pads electrically conductively connecting to at least one contact pad of the first set of board contact pads.

2. An integrated circuit testing arrangement, comprising:
an integrated circuit under an electrostatic discharge test comprising a plurality of integrated circuit contact pads;
a test board comprising a plurality of test board contact pads,
a fan-out board comprising:
a first set of board contact pads arranged on a first side of the fan-out board, the contact pads of the first set of board contact pads electrically conductively connecting to the integrated circuit contact pads of the integrated circuit under test;
a fan-out region on the first side of the fan-out board, the fan-out region comprising one or more fan-out contact pads configured to at least one of receive a test signal and provide a measurement signal; at least one contact pad of the one or more fan-out contact pads electrically conductively connecting to at least one contact pad of the first set of board contact pads;
a second set of board contact pads on a second side of the fan-out board, the contact pads of the second set of board contact pads electrically connecting to the test board contact pads of the test board, at least one contact pad of the second set of board contact pads electrically conductively connecting to at least one contact pad of the first set of board contact pads; and
at least one via extending through the fan-out board to electrically conductively connect the first set of board contact pads to the second set of board contact pads.

3. The integrated circuit testing arrangement of claim 2 ,
wherein the integrated circuit is disposed over the first side of the fan-out board; and
wherein the test board is disposed over the second side of the fan-out board.

4. The integrated circuit testing arrangement of claim 2 ,
wherein the test board comprises a system verification board configured to enable the operation of the integrated circuit under test.

5. The integrated circuit testing arrangement of claim 2 , further comprising:
a testing device electrically coupled to at least one contact pad of the one or more fan-out contact pads to provide and analyze one or more test signals while the integrated circuit under test is operated by the test board.

6. The integrated circuit testing arrangement of claim 5 ,
the fan-out board configured to inject one of a voltage and a current provided by the testing device into at least one contact pad of the integrated circuit under test.

7. The integrated circuit testing arrangement of claim 5 ,
the fan-out board configured to inject an electro static discharge test signal provided by the testing device into at least one contract pad of the integrated circuit under test.

8. The integrated circuit testing arrangement of claim 2 , further comprising:
a spacer board disposed between the test board and the fan-out board to provide a spacing between the test board and the fan-out board, the spacer board comprising a wiring structure electrically connecting each contact pad of the second set of fan-out board contact pads to the respective contact pad of the test board contact pads.

9. The integrated circuit testing arrangement of claim 8 ,
wherein the wiring structure of the spacer board comprises:
a first set of spacer board contact pads on a first side of the spacer board facing towards the fan-out board, the positions of the contact pads of the first set of spacer board contact pads matching to the positions of the contact pads of the second set of board contact pads of the fan-out board;
a second set of spacer board contact pads on a second side of the spacer board facing towards the test board, the positions of the contact pads of the second set of spacer board contact pads matching to the positions of the test board contact pads of the test board; and
a plurality of vias extending from the first side of the spacer board to the second side of the spacer board electrically connecting each contact pad of the first set of spacer board contact pads to a respective contact pad of the second set of spacer board contact pads.

10. The integrated circuit testing arrangement of claim 7 ,
the positions of the contact pads of the second set of board contact pads matching to the positions of the contact pads of the first set of spacer board contact pads.

11. The integrated circuit testing arrangement of claim 2 ,
the positions of the contact pads of the first set of board contact pads matching to the positions of the contact pads of the integrated circuit contact pads.

12. The integrated circuit testing arrangement of claim 2 ,
the positions of the contact pads of the second set of board contact pads matching to the positions of the contact pads of the test board contact pads.

13. The integrated circuit testing arrangement of claim 6 ,
wherein the spacer board has a thickness of at least 0.5 mm.

14. The integrated circuit testing arrangement of claim 2 , further comprising:
a flexible interposer structure disposed between the test board and the fan-out board comprising a plurality of vias electrically connecting the contact pads of the second set of board contact pads and the test board contact pads.

15. A method for operating an integrated circuit, the method comprising:
electrically conductively connecting the integrated circuit to a test board via a fan-out board; wherein the fan-out board comprises at least one via extending therethrough to electrically conductively connect a first set of board contact pads to a second set of board contact pads;
injecting at least one test signal into the integrated circuit by injecting the at least one test signal into at least one fan-out contact pad of the fan-out board; wherein the at least one fan-out contact pad of the fan-out board is electrically conductively connected to at least one contact pad of the first set of board contact pads; and
operating the integrating circuit using the test board.

16. The method of claim 15 , further comprising:
operating the integrated circuit via the test board.

17. The method of claim 15 ,
wherein injecting at least one signal into the integrated circuit under test comprises injecting a transmission line pulse as an electrostatic discharge stress signal.

18. The method of claim 15 , further comprising:
detecting a test signal from the integrated c

Assignees

• Intel Ip Corp

Inventors

• Orr Benjamin
• Gossner Harald

Classifications

• H05K2201/10378

  Interposers · CPC title

• H05K2201/09227

  Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting · CPC title

• H05K1/11

  Printed elements for providing electric connections to or between printed circuits · CPC title

• H05K1/0268

  for electrical inspection or testing · CPC title

• G01R31/002

  where the device under test is an electronic circuit · CPC title