Pixel receiver with capacitance cancellation for ultrasonic imaging apparatus

Patent metadata

Field	Value
Publication number	US-10004432-B2
Application number	US-201514842826-A
Country	US
Kind code	B2
Filing date	Sep 1, 2015
Priority date	Sep 1, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

An apparatus, such as a pixel sensor for an ultrasonic imaging apparatus, is disclosed. The apparatus includes a first metallization layer coupled to a piezoelectric layer, wherein a first voltage is formed at the first metallization layer in response to an ultrasonic wave reflecting off an item-to-be-imaged (e.g., a user's fingerprint) and propagating through the piezoelectric layer, and wherein the first metallization layer is situated above a substrate; a second metallization layer situated between the first metallization layer and the substrate; and a device configured to apply a second voltage to the second metallization layer to reduce a parasitic capacitance between the first metallization layer and the substrate.

First claim

What is claimed is:

1. An apparatus, comprising:
a first metallization layer coupled to a piezoelectric layer, wherein a first voltage is formed at the first metallization layer in response to an ultrasonic wave reflecting off an item-to-be-imaged and propagating through the piezoelectric layer, and wherein the first metallization layer is situated above a substrate;
a second metallization layer situated between the first metallization layer and the substrate, wherein the first metallization layer has a first area smaller than a second area of the second metallization layer; and
a device configured to apply a second voltage to the second metallization layer to reduce a parasitic capacitance between the first metallization layer and the substrate.

2. The apparatus of claim 1 , wherein the device is implemented on a CMOS IC comprising the substrate and the first and second metallization layers, and wherein the first and second metallization layers comprise top and second-from-the-top metallization layers of the CMOS IC, respectively.

3. The apparatus of claim 1 , wherein the device comprises a buffer amplifier including an input coupled to the first metallization layer and an output coupled to the second metallization layer.

4. The apparatus of claim 1 , wherein the device comprises a source-follower amplifier including a field effect transistor (FET) having a gate coupled to the first metallization layer and a source coupled to the second metallization layer.

5. The apparatus of claim 4 , wherein the gate of the FET is coupled to the first metallization layer by way of a metallization pad formed in the second metallization layer, wherein the metallization pad is electrically isolated from another portion of the second metallization layer.

6. The apparatus of claim 4 , wherein the source of the FET is coupled to the second metallization layer by way of a metallized via hole.

7. The apparatus of claim 4 , wherein the source of the FET is coupled to the second metallization layer by way of a metallization pad formed in a third metallization layer, wherein the third metallization layer is situated between the second metallization layer and the substrate.

8. The apparatus of claim 1 , wherein the second voltage is substantially the same as the first voltage.

9. The apparatus of claim 1 , wherein the second metallization layer is configured such that all vertical linear paths from the first metallization layer to the substrate intersect with the second metallization layer.

10. A method, comprising:
generating a first voltage at a first metallization layer in response to an ultrasonic wave reflecting off an item-to-be-imaged and propagating through the piezoelectric layer, wherein the first metallization layer is situated above a substrate;
generating a second voltage from the first voltage; and
applying the second voltage to a second metallization layer to reduce a parasitic capacitance between the first metallization layer and the substrate, wherein the second metallization layer is situated between the first metallization layer and the substrate, and the first metallization layer has a first area smaller than a second area of the second metallization layer.

11. The method of claim 10 , wherein a CMOS IC comprises the substrate and the first and second metallization layers, and wherein the first and second metallization layers comprise top and second-from-the-top metallization layers of the CMOS IC, respectively.

12. The method of claim 10 , wherein applying the second voltage to the second metallization layer comprises amplifying the first voltage using a buffer amplifier to generate the second voltage.

13. The method of claim 10 , wherein applying the second voltage to the second metallization layer comprises amplifying the first voltage using a source-follower amplifier including a field effect transistor (FET), wherein the FET includes a gate receiving the first voltage and a source generating the second voltage.

14. The method of claim 13 , wherein the gate of the FET is coupled to the first metallization layer by way of a metallization pad formed in the second metallization layer, wherein the metallization pad is electrically isolated from another portion of the second metallization layer.

15. The method of claim 13 , wherein the source of the FET is coupled to the second metallization layer by way of a metallized via hole.

16. The method of claim 13 , wherein the source of the FET is coupled to the second metallization layer by way of a metallization pad formed in a third metallization layer, wherein the third metallization layer is situated between the second metallization layer and the substrate.

17. The method of claim 10 , wherein the second voltage is substantially the same as the first voltage.

18. The method of claim 10 , wherein the second metallization layer is configured such that all vertical linear paths from the first metallization layer to the substrate intersect with the second metallization layer.

19. An apparatus, comprising:
means for generating a first voltage at a first metallization layer in response to an ultrasonic wave reflecting off an item-to-be-imaged and propagating through the piezoelectric layer, wherein the first metallization layer is situated above a substrate;
and
means for applying a second voltage to a second metallization layer to reduce a parasitic capacitance between the first metallization layer and the substrate, wherein the second metallization layer is situated between the first metallization layer and the substrate, and the first metallization layer has a first area smaller than a second area of the second metallization layer.

20. The apparatus of claim 19 , wherein a CMOS IC comprises the substrate and the first and second metallization layers, and wherein the first and second metallization layers comprise top and second-from-the-top metallization layers of the CMOS IC, respectively.

21. The apparatus of claim 19 , wherein the means for applying the second voltage to the second metallization layer comprises means for amplifying the first voltage to generate the second voltage.

22. The apparatus of claim 19 , wherein the means for applying the second voltage to the second metallization layer comprises means for amplifying the first voltage using source-follower including a field effect transistor (FET), wherein the FET includes a gate receiving the first voltage and a source generating the second voltage.

23. The apparatus of claim 22 , wherein the gate of the FET is coupled to the first metallization layer by way of a metallization pad formed in the second metallization layer, wherein the metallization pad is electrically isolated from another portion of the second metallization layer.

24. The apparatus of claim 22 , wherein the source of the FET is coupled to the second metallization layer by way of a metallized via hole.

25. The apparatus of claim 22 , wherein the source of the FET is coupled to the second metallization layer by way of a metallization pad formed in a third metallization layer, wherein the third metallization layer is situated between the second metallization layer and the substrate.

26. The apparatus of claim 19 , wherein the second voltage is substantially the same as the first voltage.

27. The apparatus of claim 19 , wherein the second metallization layer is configured such that all vertical linear paths from the f

Assignees

• Qualcomm Inc

Inventors

• Mathe Lennart Karl-Axel
• Wadhwa Sameer
• Xia Lingli

Classifications

• G01S7/52079 Primary

  Constructional features (constructional features of transducers B06B; mounting transducers G10K11/00; constructional features of ultrasonic medical diagnostic devices A61B8/44) · CPC title

• G01S15/8906

  Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques · CPC title

• A61B5/117 Primary

  Identification of persons (methods or arrangements for recognising patterns, e.g. fingerprints, G06F18/00, G06V40/00; identification of persons by analysing their voice or speech G10L17/00) · CPC title

• H03K17/975

  using a capacitive movable element · CPC title

• G06K9/0002

  Physics · mapped topic