Printed circuit board assembly

Patent metadata

Field	Value
Publication number	US-10004137-B2
Application number	US-201715408672-A
Country	US
Kind code	B2
Filing date	Jan 18, 2017
Priority date	Mar 22, 2016
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

The present invention provides a printed circuit board assembly including a substrate having a plurality of conductive layers vertically sandwiched between a first cap-insulation layer and a second cap-insulation layer. The substrate has a first part, a second part and a third part. For protecting the conductive layers from moisture, each of the areas of the conductive layers corresponding to the second part is smaller than the area of the first cap-insulation layer corresponding to the second part for at least a first predetermined percentage, and each of the areas of the conductive layers corresponding to the second part is smaller than the area of the second cap-insulation layer corresponding to the second part for at least the first predetermined percentage.

First claim

What is claimed is:

1. A printed circuit board assembly, comprising:
a substrate, comprising:
a first cap-insulation layer;
a second cap-insulation layer;
a plurality of conductive layers, vertically sandwiched between the first cap-insulation layer and the second cap-insulation layer, wherein the substrate has a first part, a second part and a third part, and the second part is laterally sandwiched between the first part and the third part along a longitudinal direction, wherein for protecting the conductive layers from moisture, each of the areas of the conductive layers corresponding to the second part is smaller than the area of the first cap-insulation layer corresponding to the second part for at least a first predetermined percentage, and each of the areas of the conductive layers corresponding to the second part is smaller than the area of the second cap-insulation layer corresponding to the second part for at least the first predetermined percentage;
a first connector implemented in the first part; and
a second connector implemented in the third part, wherein the first cap-insulation layer and the second cap-insulation layer has a plurality of vias, wherein the region under the first connector is a first region, the region under the second connector is a second region, and the region except for the first region and the second region in the first part, the second part and the third part is a third region, wherein density of the vias on the first cap-insulation layer corresponding to the second region and density of vias on the second cap-insulation layer corresponding to the second region are larger than density of the vias on the first cap-insulation layer corresponding to the third region and density of vias on the second cap-insulation layer corresponding to the third region.

2. The printed circuit board assembly as claimed in claim 1 , wherein each of the areas of the conductive layers corresponding to the first part is smaller than the area of the first cap-insulation layer corresponding to the first part for at least a second predetermined percentage, each of the areas of the conductive layers corresponding to the first part is smaller than the area of the second cap-insulation layer corresponding to the first part for at least the second predetermined percentage, each of the areas of the conductive layers corresponding to the third part is smaller than the area of the first cap-insulation layer corresponding to the third part for at least the third predetermined percentage, and each of the areas of the conductive layers corresponding to the third part is smaller than the area of the second cap-insulation layer corresponding to the third part for at least the third predetermined percentage.

3. The printed circuit board assembly as claimed in claim 2 , wherein the first predetermined percentage, the second predetermined percentage and the third predetermined percentage are each ten percent.

4. The printed circuit board assembly as claimed in claim 1 , wherein
the first connector is coupled to a device under test; and
the second connector is coupled to a host.

5. The printed circuit board assembly as claimed in claim wherein density of the vias on the first cap-insulation layer corresponding to the first region and the density of the vias on the second cap-insulation layer corresponding to the first region are larger than density of the vias on the first cap-insulation layer corresponding to the third region and density of the vias on the second cap-insulation layer corresponding to the third region.

6. The printed circuit board assembly as claimed in claim 5 , wherein the first connector and the second connector cover the vias on the first cap-insulation layer and the second cap-insulation layer corresponding to the first region and the second region.

7. The printed circuit board assembly as claimed in claim 1 , wherein the first cap-insulation layer corresponding to the third region and the second cap-insulation layer corresponding to the third region do not have any vias.

8. A printed circuit board assembly, comprising:
a substrate, comprising:
a first cap-insulation layer;
a second cap-insulation layer; and
a plurality of conductive layers, vertically sandwiched between the first cap-insulation layer and the second cap-insulation layer, wherein the substrate has a first part, a second part and a third part, the second part is laterally sandwiched between the first part and the third part along a longitudinal direction, wherein for protecting the conductive layers from moisture, sides of each of the conductive layers that corresponds to the second part and is vertical to the longitudinal direction has a distance that is greater than a first predetermined distance from sides of the first cap-insulation layer and the second cap-insulation layer that corresponds to the second part and is vertical to the longitudinal direction, wherein the first predetermined distance is more than 0.5 cm.

9. The printed circuit board assembly as claimed in claim 8 , wherein sides of each of conductive layers that corresponds to the first part and verticals to the longitudinal direction has a distance that is greater than a second predetermined distance from sides of the first cap-insulation layer and the second cap-insulation layer that corresponds to the first part and verticals to the longitudinal direction, and sides of each of the conductive layers that corresponds to the third part and vertical to the longitudinal direction have a distance that is greater than a third predetermined distance from sides of the first cap-insulation layer and the second cap-insulation layer that corresponds to the third part and verticals to the longitudinal direction.

10. The printed circuit board assembly as claimed in claim 9 , wherein the second predetermined distance and the third predetermined distance are more than 0.5 cm.

11. The printed circuit board assembly as claimed in claim 8 , further comprising: a first connector, implemented in the first part and coupled to a device under test; and
a second connector, implemented in the third part and coupled to a host, wherein the first cap-insulation layer and the second cap-insulation layer have a plurality of vias, wherein the region under the first connector is a first region, the region under the second connector is a second region, and the region except for the first region and the second region in the first part, the second part and the third part is a third region.

12. The printed circuit board assembly as claimed in claim 11 , wherein density of the vias on the first cap-insulation layer corresponding to the second region and density of vias on the second cap-insulation layer corresponding to the second region are larger than density of the vias on the first cap-insulation layer corresponding to the third region and density of vias on the second cap-insulation layer corresponding to the third region.

13. The printed circuit board assembly as claimed in claim 12 , wherein density of the vias on the first cap-insulation layer corresponding to the first region and the density of the vias on the second cap-insulation layer corresponding to the first region are larger than density of the vias on the first cap-insulation layer corresponding to the third region and density of the vias on the second cap-insulation layer corresponding to the third region.

14. The printed circuit board assembly as claimed in claim 13 , wherein the first connector and the second connector cover all of the vias on the first cap-insulation layer and the second cap-insulation layer corresponding to the first region and the second r

Assignees

• Silicon Motion Inc

Inventors

• Huang I-Hung

Classifications

• H05K1/0271 Primary

  Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K2201/09972

  Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently · CPC title

• H05K3/284 Primary

  for encapsulating mounted components (H05K1/185 takes precedence) · CPC title

• G01R1/0416

  Connectors, terminals (G01R1/0425 and G01R1/0433 take precedence; with measurement function for battery poles G01R31/364) · CPC title