Clock generator

Patent metadata

Field	Value
Publication number	US-10003344-B2
Application number	US-201615009405-A
Country	US
Kind code	B2
Filing date	Jan 28, 2016
Priority date	Nov 21, 2011
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a clock generator, for generating a continuous output clock signal, the clock generator comprising:
a first clock signal input, for receiving a first input clock signal; and
a second clock signal input, for receiving a second input clock signal;

at least one digital audio interface, for receiving digital audio data with an accompanying audio data clock;
a digital-analog converter, for reconstructing analog audio data based on received digital audio data;
wherein the audio data clock is provided to the clock generator as the first input clock signal, and the output clock signal of the clock generator is used as a clock for the digital-analog converter;
wherein the received digital audio data and accompanying audio data clock are received by the digital audio interface in burst mode, and the digital-analog converter is continuously supplied with the output clock signal of the clock generator, and the output clock signal of the clock generator is based on the first input clock signal and the second input clock signal; and
wherein the clock generator further comprises:
a first frequency comparator, for generating a first frequency comparison signal based on a ratio of a frequency of the output clock signal to a frequency of the first input clock signal;
a first subtractor, for forming a first error signal representing a difference between an input desired frequency ratio and the first frequency comparison signal;
a first digital filter, for receiving the first error signal and forming a filtered first error signal;
a second frequency comparator, for generating a second frequency comparison signal based on a ratio of a frequency of the output clock signal to a frequency of the second input clock signal;
a second subtractor, for forming a second error signal representing a difference between the filtered first error signal and the second frequency comparison signal;
a second digital filter, for receiving the second error signal and forming a filtered second error signal; and
a numerically controlled oscillator, for receiving the filtered second error signal and generating the output clock signal.

2. An integrated circuit as claimed in claim 1 , comprising first and second digital audio interfaces, for receiving respective first and second digital audio data streams with respective accompanying first and second audio data clocks, wherein the first or second audio data clock may be selectably provided to the clock generator as the first input clock signal.

3. An integrated circuit as claimed in claim 2 , comprising a multiplexer connected to receive the first and second audio data clocks, wherein an output of the multiplexer is connected to the clock generator to provide the first input clock signal.

4. An integrated circuit as claimed in claim 2 , wherein the first and second digital audio interfaces are connected to an applications processor and a communications processor.

5. An integrated circuit as claimed in claim 2 , further comprising a third digital audio interface, for receiving a third digital audio data stream.

6. An integrated circuit as claimed in claim 1 , wherein the received digital audio data and accompanying audio data clock are received from a USB source.

7. An integrated circuit as claimed in claim 1 , further comprising storage circuitry, for storing the received digital audio data and passing it to the digital-analog converter.

8. An integrated circuit as claimed in claim 1 , further comprising an output terminal, for supplying the reconstructed analog audio data as an output of the integrated circuit.

9. An integrated circuit as claimed in claim 1 , wherein the integrated circuit comprises an audio and/or video codec.

10. A device comprising an integrated circuit, wherein the integrated circuit comprises:
a clock generator, for generating a continuous output clock signal, the clock generator comprising a first clock signal input, for receiving a first input clock signal; and a second clock signal input, for receiving a second input clock signal;
at least one digital audio interface, for receiving digital audio data with an accompanying audio data clock;
a digital-analog converter, for reconstructing analog audio data based on received digital audio data;
wherein the audio data clock is provided to the clock generator as the first input clock signal, and the output clock signal of the clock generator is used as a clock for the digital-analog converter; and
wherein the received digital audio data and accompanying audio data clock are received by the digital audio interface in burst mode, and the digital-analog converter is continuously supplied with the output clock signal of the clock generator, and the output clock signal of the clock generator is based on the first input clock signal and the second input clock signal; and
wherein the clock generator further comprises:
a first frequency comparator, for generating a first frequency comparison signal based on a ratio of a frequency of the output clock signal to a frequency of the first input clock signal;
a first subtractor, for forming a first error signal representing a difference between an input desired frequency ratio and the first frequency comparison signal;
a first digital filter, for receiving the first error signal and forming a filtered first error signal;
a second frequency comparator, for generating a second frequency comparison signal based on a ratio of a frequency of the output clock signal to a frequency of the second input clock signal;
a second subtractor, for forming a second error signal representing a difference between the filtered first error signal and the second frequency comparison signal;
a second digital filter, for receiving the second error signal and forming a filtered second error signal; and
a numerically controlled oscillator, for receiving the filtered second error signal and generating the output clock signal.

11. A device as claimed in claim 10 , further comprising a crystal oscillator, connected to the second clock signal input of the clock generator.

12. A device as claimed in claim 10 , further comprising a speaker connected to an output terminal of the integrated circuit.

13. A device as claimed in claim 10 , wherein the integrated circuit comprises first and second digital audio interfaces, for receiving respective first and second digital audio data streams with respective accompanying first and second audio data clocks, wherein the first or second audio data clock may be selectably provided to the clock generator as the first input clock signal.

14. A device as claimed in claim 13 , comprising an applications processor and a communications processor connected to the first and second digital audio interfaces.

15. A device as claimed in claim 14 , further comprising RF front-end circuitry connected to the communications processor.

16. A device as claimed in claim 13 , wherein the integrated circuit comprises a third digital audio interface, for receiving a third digital audio data stream.

17. A device as claimed in claim 16 , further comprising a Bluetooth™ transceiver, an FM radio, a Wi-Fi transceiver, a High Definition Multimedia Interface, and S/PDIF interface or a USB interface, connected to the third digital audio interface of the integrated circuit.

18. A device as claimed in claim 10 , wherein the device is a smartphone, games console, tablet, laptop computer, desktop computer, or hi-fi system.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Lesso John Paul

Classifications

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/14

  for assuring constant frequency when supply or correction voltages fail · CPC title

• H03G5/00

  Tone control or bandwidth control in amplifiers · CPC title

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title