System, method and apparatus having improved pulse width modulation frequency resolution

Patent metadata

Field	Value
Publication number	US-10003329-B2
Application number	US-201514714315-A
Country	US
Kind code	B2
Filing date	May 17, 2015
Priority date	Jun 28, 2007
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

Using a combination of frequency dithering of a PWM counter and a variable time delay circuit yields improved PWM frequency resolution with realizable circuit components and clock operating frequencies. A controllable time delay circuit lengthens a PWM signal during the first PWM cycle. During the second PWM cycle, the PWM period is increased beyond the desired amount, but the delay is reduced during this second PWM cycle to achieve the correct (desired) PWM signal period. The dithering of the PWM signal period enables the time delay circuit to be “reset” so that an infinite delay circuit is not required. The time delay circuit provides short term (one cycle) frequency adjustment so that the resulting PWM cycle is not dithered and has a period at the desired frequency resolution.

First claim

What is claimed is:

1. An apparatus having improved pulse width modulation frequency resolution, said apparatus comprising:
a pulse width modulation circuit operable to generate a pulse width modulation signal comprising a first and a second period;
a delay circuit delaying said pulse width modulation signal;
a multiplexer receiving said pulse width modulation signal and said delayed pulse width modulation signal; and
control logic coupled with said multiplexer, the control logic for:
selecting either said pulse width modulation signal or said delayed pulse width modulation signal depending on the selected period of said pulse width modulation signal, wherein the pulse width modulated output signal of said multiplexer has a third period which lies between said first and second period; and
selecting in alternating sequence said pulse width modulation signal and said delayed pulse width modulation signal to generate the pulse width modulated output signal of said multiplexer with the third period which lies between said first and second period.

2. The apparatus according to claim 1 , comprising:
a period register for storing a pulse width modulation period value wherein the control logic is coupled to a least significant bit of the period register;
a plus one effective period adder coupled to the period register and having a carry-in input coupled to the control logic, wherein when the carry-in input is at a first logic level, one is added to the PWM period value;
a period comparator coupled to the plus one effective period adder and receiving the PWM period value when the carry-in input is at a second logic level and the PWM period value plus one when the carry-in input is at the first logic level;
a clock counter for counting clock pulses from a clock source, the clock counter being coupled to the period comparator, wherein the period comparator is configured to:
compare a clock count from the clock counter with the PWM period value or the PWM period value plus one from the plus one effective period adder; and
reset the clock counter when the clock count is greater than or equal to the PWM period value or the PWM period value plus one to generate said first or second period;

a duty cycle register for storing a PWM duty cycle;
a duty cycle comparator coupled to the clock counter and the duty cycle register, wherein the duty cycle comparator is configured to compare the PWM duty cycle to the clock count and whenever the clock count is less than or equal to the PWM duty cycle a first logic level is generated from an output of the duty cycle comparator;
a delay element coupled to the output of the duty cycle comparator, wherein the delay element is configured to delay the first PWM signal from the duty cycle comparator; and
a multiplexer coupled to the delay element and the output of the duty cycle comparator, wherein either a delayed first PWM signal or non-delayed first PWM signal is configured to be selected to produce a second PWM signal from an output of the multiplexer;
wherein:
the delay circuit comprises a delay flip-flop coupled to the control logic and the multiplexer, wherein the delay flip-flop states are configured to be controlled by the control logic depending on whether the delayed first PWM signal or the non-delayed first PWM signal was last selected; and
the delay flip-flop is configured to generate a multiplexer control signal for selection of either the delayed first PWM signal or the non-delayed first PWM signal, whereby the second PWM signal has a PWM period resolution substantially equal to a time delay of the delay element.

3. The apparatus according to claim 2 , wherein the clock count time period is configured to be substantially twice the time period of the delay element time delay.

4. The apparatus according to claim 2 , further comprising a power charging circuit for use as a switch mode power supply.

5. The apparatus according to claim 4 , further comprising electronic circuits powered by the switch mode power supply, wherein the electronic circuits and the switch mode power supply are used in an electronic system.

6. The apparatus according to claim 1 , comprising:
a period register for storing a pulse width modulation period value, the period register having m bits of which n bits are least significant;
a delay adder coupled to the n least significant bits of the period register;
a delay register coupled to the delay adder, wherein a value from the delay adder is stored in the delay register each time the delay register is clocked;
a plus one effective period adder coupled to the period register and a carry-out from the delay adder, wherein when the carry-out from the delay adder is at a first logic level, the plus one effective period adder is configured to add one to the PWM period value from the period register;
a period comparator coupled to the plus one effective period adder and configured to:
receive the PWM period value when the carry-out from the delay adder is at a second logic level; and
receive the PWM period value plus one when the carry-out from the delay adder is at the first logic level;

a clock counter for counting clock pulses from a clock source, the counter being coupled to the period comparator, wherein the period comparator is configured to compare a clock count from the clock counter with the PWM period value or the PWM period value plus one from the plus one effective period adder, whereby the period comparator is configured to reset the clock counter and clocks the delay register when the clock count is greater than or equal to the PWM period value or the PWM period value plus one;
a duty cycle register for storing a PWM duty cycle;
a duty cycle comparator coupled to the clock counter and the duty cycle register, wherein the duty cycle comparator is configured to compare the PWM duty cycle to the clock count and whenever the clock count is less than or equal to the PWM duty cycle a first logic level is generated from an output of the duty cycle comparator; and
a plurality of multi-tap delay elements, the plurality of multi-tap delay elements are coupled in series and configured to produce a plurality of time delays of the first PWM signal from the duty cycle comparator, a first one of the plurality of multi-tap delay elements being coupled to the output of the duty cycle comparator;
wherein the multiplexer is coupled to the plurality of multi-tap delay elements, the output of the duty cycle comparator and an output of the delay adder, wherein the output of the delay adder is configured to control selection of which one of the plurality of multi-tap delay elements is coupled to an output of the multiplexer to produce a second PWM signal, whereby the second PWM signal has a PWM period resolution substantially equal to a time delay of a single one of the plurality of multi-tap delay elements.

7. The apparatus according to claim 6 , further comprising a power charging circuit for use as a switch mode power supply.

8. The apparatus according to claim 6 , wherein the clock count time period is configured to be substantially 2 n times the time period of the delay element time delay.

9. The apparatus according to claim 1 , further comprising a power charging circuit for use as a switch mode power supply.

10. The apparatus according to claim 9 , further comprising electronic circuits powered by the switch mode power supply, wherein the electronic circuits and the switch mode power supply are used in an electronic system.

11. An apparatus having improved pulse width modulation frequency resolution, said apparatus comprising:
a pulse width modulation circuit operable to generate a pulse width modulation signal comprisi

Assignees

• Microchip Tech Inc

Inventors

• Kris Bryan

Classifications

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03M1/822

  using pulse width modulation · CPC title