Semiconductor devices and methods for dead time optimization by measuring gate driver response time

Patent metadata

Field	Value
Publication number	US-10003260-B2
Application number	US-201514747981-A
Country	US
Kind code	B2
Filing date	Jun 23, 2015
Priority date	Jun 23, 2015
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

Switching control devices and related operating methods are provided. An exemplary electronic device includes a semiconductor die, a driver arrangement on the semiconductor die to generate a switch control output signal based on an input switching command signal, and a timer arrangement on the semiconductor die and coupled to the driver arrangement to measure a time difference between a first change in the command signal and an exhibited response in the switch control signal, which can then be utilized to achieve a desired dead time.

First claim

What is claimed is:

1. An electronic device comprising:
a semiconductor die;
an output interface;
a driver arrangement on the semiconductor die and coupled to the output interface, the driver arrangement comprising first driver circuitry to generate a switch control signal at the output interface based on an input command signal and second driver circuitry to generate a second switch control signal based on a second command signal;
a timer arrangement on the semiconductor die and coupled to the driver arrangement to measure a turn on delay associated with a first switching element coupled to the first driver circuitry of the driver arrangement based on a time difference between a first change in the input command signal and a second response to the first change in the switch control signal at the output interface and measure a turn off delay associated with a second switching element coupled to the second driver circuitry based on a second time difference between a third change in the second command signal and a fourth change in the second switch control signal;
a lookup table including characteristic values for the first switching element;
a register on the semiconductor die and coupled to the timer arrangement to store one or more of the turn on delay and the turn off delay; and
control circuitry on the semiconductor die and coupled to the lookup table and the register to:
determine a switch characteristic value for the first switching element based at least in part on current operating conditions utilizing the lookup table;
determine a timing for a subsequent change in the input command signal based at least in part on the switch characteristic value, a difference between the turn on delay and the turn off delay, and a target dead time, wherein the subsequent change in the input command signal is adjusted based on the determined timing.

2. The electronic device of claim 1 , further comprising a second register to store the target dead time, wherein the control circuitry is coupled to the second register.

3. The electronic device of claim 1 , further comprising a pulse generation arrangement coupled between the driver arrangement and the control circuitry to generate the input command signal based on the timing.

4. The electronic device of claim 1 , wherein the timer arrangement automatically accrues a timer value in response to the first change in the input command signal and automatically stops accrual of the timer value in response to the second response in the switch control signal.

5. The electronic device of claim 4 , wherein the register stores the timer value after the second response in the switch control signal.

6. The electronic device of claim 1 , further comprising a pulse generation arrangement fabricated on the semiconductor die, wherein the pulse generation arrangement is coupled between the driver arrangement and the control circuitry to generate the input command signal based on the timing.

7. The electronic device of claim 1 , wherein the control circuitry determines an offset for the subsequent change in the input command signal relative to a fifth change in the second command signal based at least in part on the target dead time and the difference between the turn on delay and the turn off delay.

8. The electronic device of claim 1 , wherein the output interface comprises a terminal of an electronic device package including the semiconductor die.

9. The electronic device of claim 8 , further comprising a control register on the semiconductor die to store the target dead time, wherein the control circuitry is coupled to the control register.

10. The electronic device of claim 1 , further comprising a control register on the semiconductor die to store the target dead time, wherein the control circuitry is coupled to the control register.

11. A method of operating switching circuitry comprising a first switching element and a second switching element, the method comprising:
measuring, by a timer arrangement on a semiconductor die, a turn on delay associated with first driver circuitry on the semiconductor die based on a first time difference between a first change in a first input command signal to the first driver circuitry and a second change in a first output signal at a first output interface coupled to the first driver circuitry, the first output interface being coupled to the first switching element and the first driver circuitry generating the first output signal in response to the first input command signal;
measuring, by the timer arrangement, a turn off delay associated with second driver circuitry on the semiconductor die based on a second time difference between a third change in a second input command signal to the second driver circuitry and a fourth change in a second output signal at a second output interface coupled to the second driver circuitry, the second output interface being coupled to the second switching element and the second driver circuitry generating the second output signal in response to the second input command signal;
storing, by a first register on the semiconductor die, the turn on delay;
storing, by a second register on the semiconductor die, the turn off delay;
determining, by control circuitry on the semiconductor die, a switch characteristic value for the first switching element based at least in part on current operating conditions utilizing a lookup table; and
determining, by control circuitry on the semiconductor die, an offset for a subsequent change in the first input command signal provided to the first driver circuitry for operating the first switching element based on the switch characteristic value, a difference between the turn on delay and the turn off delay, and a targeted dead time, wherein the offset is applied on subsequent first input command signals.

12. The method of claim 11 , further comprising wherein determining the offset comprises determining the offset for assertion of the first input command signal relative to deassertion of the second input command signal provided to the second driver circuitry based on the targeted dead time and the difference between the turn on delay and the turn off delay.

13. The method of claim 12 , further comprising:
measuring, by the timer arrangement, a second turn on delay associated with the second driver circuitry;
measuring, by the timer arrangement, a second turn off delay associated with the first driver circuitry; and
determining a second offset for assertion of the second input command signal provided to the second driver circuitry for operating the second switching element relative to deassertion of the first input command signal based on the targeted dead time and a second difference between the second turn on delay and the second turn off delay.

14. A semiconductor device comprising:
a first output interface;
a second output interface;
first driver circuitry on the semiconductor die to generate a first output voltage signal at the first output interface in response to a first input command signal;
second driver circuitry on the semiconductor die to generate a second output voltage signal at the second output interface in response to a second input command signal;
a timer arrangement on the semiconductor die and coupled to the driver arrangement to measure:
a first time difference between a first change in the first input command signal and a second change in the first output voltage signal at the first output interface, and
a second time difference between a third change in the second input command and a fourth change the second output voltage signal at the second output interface;

a first re

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Rowald Dirk
• Bode Hubert M

Classifications

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M1/38

  Means for preventing simultaneous conduction of switches · CPC title

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H03K17/284

  in field effect transistor switches · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title