Inrush control with multiple switches

Patent metadata

Field	Value
Publication number	US-10003190-B2
Application number	US-201414300999-A
Country	US
Kind code	B2
Filing date	Jun 10, 2014
Priority date	Jul 12, 2013
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

A novel system is offered for supplying power from an input node to a load coupled to an output node. The system may have multiple switches coupled between the input node and the output node. One or more limiting circuits may be configured for controlling the switches so as to limit outputs of the switches. For example, the limiting circuits may limit current through the respective switches. One or more timers may set a delay period for indicating a fault condition after the limiting is initiated.

First claim

What is claimed is:

1. A system for supplying power from an input node to a load coupled to an output node, comprising:
a first limiting circuit configured to control a first switch so as to limit an output current of the first switch,
a second limiting circuit configured to control a second switch, independent of the first limiting circuit, so as to limit an output current of the second switch in an amount that is different than the limit imposed by the first limiting circuit on an output of the first switch, and
a logic circuit configured to produce an output signal responsive to the output current of the first switch being limited by the first limiting circuit and the output current of the second switch being limited by the second limiting circuit.

2. The system of claim 1 , wherein the first limiting circuit limits current through the first switch, and the second limiting circuit limits current through the second switch.

3. The system of claim 1 further comprising a timer circuit responsive to the output signal of the logic circuit for indicating a fault condition after expiration of a delay period.

4. The system of claim 3 , wherein both the first and second switches are turned off after expiration of the delay period.

5. The system of claim 1 , further comprising a first current sense element for sensing a current in the first switch, and a second current sense element for sensing the current in the second switch.

6. The system of claim 5 , wherein the first limiting circuit is responsive to the current sensed by the first current sense element, and the second limiting circuit is responsive to the current sensed by the second current sense element.

7. The system of claim 6 , further comprising an indicative circuit for producing a path on signal indicating that a power path provided between the input node and the output node is turned on, the indicative circuit including:
a first detecting circuit for detecting that the first switch is in an on state, and
a second detecting circuit for detecting that the second switch is in an on state.

8. The system of claim 7 , wherein the indicative circuit is configured for producing the path on signal when either both the first and second switches are in an on state, or when one of the first and second switches is in an on state and a limiting circuit associated with the other of the first and second switches is limiting an output of the respective switch.

9. The system of claim 1 , wherein the first switch is coupled between the input node and the output node, and the second switch is coupled in parallel to the first switch between the input node and the output node.

10. The system of claim 1 , wherein the first and second switches are turned on or off at the same time.

11. A system for supplying power from an input node to a load coupled to an output node, comprising:
first and second switches coupled between the input node and the output node,
a first current limit circuit configured for controlling the first switch so as to limit current flowing through the first switch to a first value, and
a second current limit circuit configured for controlling the second switch so as to limit a current flowing through the second switch to a second value,
wherein the second switch is maintained in an off state when the first switch is turned on, and the second switch is turned on in response to a signal indicating that the first switch is in an on state.

12. The system of claim 11 , wherein the second switch is configured to provide a low resistance path for a load current around the first switch.

13. The system of claim 11 , further comprising a first current sense element for sensing the current in the first switch, and a second current sense element for sensing the current in the second switch, wherein sensitivity of the first current sense element is greater than sensitivity of the second current sense element.

14. The system of claim 13 , wherein the first current limit circuit is responsive to the current sensed by the first current sense element, and the second current limit circuit is responsive to the current sensed by the second current sense element.

15. The system of claim 11 , further comprising a timer circuit including:
a first timer configured to initiate a first delay period in response to a first status signal indicating that the first current limit circuit begins operation in a current limit mode to limit the current through the first switch, and
a second timer configured to initiate a second delay period in response to a second status signal indicating that the second current limit circuit begins operation in a current limit mode to limit the current through the second switch.

16. The system of claim 15 , wherein the timer circuit is configured to indicate a fault condition after expiration of the first delay period or the second delay period.

17. The system of claim 11 , further comprising an indicative circuit for producing a path on signal indicating that a power path provided between the input node and the output node is turned on, the indicative circuit is configured to produce the path on signal when the second switch is in an on state, without detecting the state of the first switch.

18. A system for supplying power from an input node to a load coupled to an output node, comprising:
first and second switches coupled between the input node and the output node, and
a limiting circuit configured for controlling the first switch so as to limit output of the first switch,
wherein the second switch is configured to be turned on only after the first switch is fully on.

19. The system of claim 18 , wherein the limiting circuit limits current through the first switch.

20. The system of claim 19 , wherein the limiting circuit is configured for controlling the first switch so as to limit current flowing through the first switch when the second switch is turned off.

21. The system of claim 18 , wherein the second switch is maintained in an off state when the first switch is turned on, and the second switch is turned on when the first switch is in an on state and a voltage across the second switch is below a threshold level.

22. The system of claim 18 , wherein the second switch is configured to provide a low resistance path for a load current around the first switch.

23. The system of claim 18 , wherein the second switch is turned off when a voltage across the second switch exceeds a threshold level.

24. The system of claim 18 , wherein the second switch is turned off when a gate to source voltage of the first switch falls below a threshold level.

25. The system of claim 18 , wherein the second switch is turned off when the first switch is turned off.

26. The system of claim 18 , further comprising an indicative circuit for producing a path on signal indicating that a power path provided between the input node and the output node is turned on, the indicative circuit is configured to produce the path on signal when the first switch is in an on state, without detecting the state of the second switch.

Assignees

• Linear Tech Corp

Inventors

• Simonson Joshua John
• Soo David Henry
• Umminger Christopher Bruce

Classifications

• H02H9/001

  limiting speed of change of electric quantities, e.g. soft switching on or off (progressive control of electronic switches for eliminating interferences H03K17/16) · CPC title

• H03K17/167

  using parallel switching arrangements · CPC title

• H02H9/025 Primary

  Current limitation using field effect transistors · CPC title

• H02H3/025

  Disconnection after limiting, e.g. when limiting is not sufficient or for facilitating disconnection · CPC title

• H02H9/004

  in connection with live-insertion of plug-in units (involving communication with a central processing unit G06F13/40) · CPC title