Shield wrap for a heterostructure field effect transistor

Patent metadata

Field	Value
Publication number	US-10002957-B2
Application number	US-201113333843-A
Country	US
Kind code	B2
Filing date	Dec 21, 2011
Priority date	Dec 21, 2011
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

Devices are disclosed for providing heterojunction field effect transistor (HFETs) having improved performance and/or reduced noise generation. A gate electrode is over a portion of the active region and is configured to modulate a conduction channel in the active region of an HFET. The active region is in a semiconductor film between a source electrode and a drain electrode. A first passivation film is over the active region. An encapsulation film is over the first passivation film. A first metal pattern on the encapsulation film includes a shield wrap over the majority of the active region and is electrically connected to the source electrode.

First claim

The invention claimed is:

1. A high-voltage field effect transistor (HFET), comprising:
a substrate;
a GaN film buffer layer formed on the substrate;
an AlGaN film disposed over a surface of the GaN film buffer layer to form a heterostructure with the GaN film buffer layer;
a conduction channel formed at a top portion of the GaN film buffer layer;
a first passivation film formed over the AlGaN film to form an interface with the AlGaN film to increase surface mobility of electrons, wherein the first passivation film forms a first portion of a gate dielectric;
a second passivation film formed over the first passivation film, wherein the second passivation film forms a second portion of the gate dielectric;
a source electrode formed on the AlGaN film;
a drain electrode formed on the AlGaN film;
an active region defined between the source electrode and the drain electrode, wherein the conduction channel is formed in the active region;
a gate electrode formed on top of the second passivation film, wherein the gate electrode is coupled to receive a gate voltage to modulate the conduction channel in the active region;
a third passivation film formed over the source electrode, the drain electrode, and the gate electrode to allow for formation of interconnects to the source electrode and the drain electrode;
a first gate field plate formed on top of the third passivation film to spread an electric field on an edge of the gate electrode closest to the drain electrode to reduce a probability that carriers are injected in the gate dielectric;
a fourth passivation film formed over the first gate field plate;
a first metal pattern formed over the fourth passivation film, wherein the first metal pattern further includes a second gate field plate;
a first source via coupled to the first metal pattern to make electrical contact to the source electrode, wherein the second gate field plate extends over the fourth passivation film;
a first drain via coupled to the first metal pattern to make electrical contact to the drain electrode;
an encapsulation film formed over the first metal pattern; and
a second metal pattern formed over the encapsulation film, wherein the second metal pattern includes:
a shield wrap disposed over the encapsulation film, wherein the shield wrap extends to overlap a surface of the HFET without creating a direct current electrical path between the source electrode and the drain electrode;
a second source via electrically connecting the shield wrap to the source electrode;
a drain connection;
a second drain via electrically connecting the drain connection to the drain electrode; and
a gap defined in the second metal pattern between the shield wrap and the drain connection.

2. The HFET of claim 1 , wherein the first passivation film comprises Al 2 O 3 , zirconium dioxide (ZrO 2 ), aluminum nitride (AlN), or hafnium oxide (HfO 2 ).

3. The HFET of claim 1 , wherein the first passivation film comprises silicon dioxide (SiO 2 ), or silicon nitride (Si 3 N 4 ).

4. The HFET of claim 1 , wherein a combined thickness of the first and second passivation films is 5 nm-20 nm.

5. The HFET of claim 1 , wherein a metal stack for the source electrode, the drain electrode, and the gate electrode comprises Al, Ni, or Ti.

6. The HFET of claim 1 , wherein a metal stack for the source electrode, the drain electrode, and the gate electrode comprises TiW, TiN, or TiAu.

7. The HFET of claim 1 , wherein a metal stack for the source electrode, the drain electrode, and the gate electrode comprises TiAlMoAu, TiAlNiAu, or TiAlPtAu.

8. The HFET of claim 1 , wherein the third passivation film comprises silicon nitride or silicon oxide.

9. The HFET of claim 1 , wherein the third passivation film is a composite film made of layers of multiple films.

10. The HFET of claim 1 , wherein the encapsulation film comprises silicon oxide, silicon nitride, or glass.

11. The HFET of claim 1 , wherein the encapsulation film comprises organic dielectrics, polyimide, or benzocyclobutene based dielectrics.

12. The HFET of claim 1 , wherein the encapsulation film is a composite film made of layers of multiple films.

13. The HFET of claim 1 , wherein the encapsulation film is 0.5 μm to 5 μm thick.

14. The HFET of claim 1 , wherein the gap is filled with SiN.

15. The HFET of claim 1 , wherein the second metal pattern has a thickness of 0.7 μm to 2 μm.

Assignees

• Koudymov Alexei
• Power Integrations Inc

Inventors

• Koudymov Alexei

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

• H01L29/2003

  Electricity · mapped topic

• H01L29/7787 Primary

  Electricity · mapped topic

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title