Low-pin microcontroller device with multiple independent microcontrollers

Patent metadata

Field	Value
Publication number	US-10002103-B2
Application number	US-201615065027-A
Country	US
Kind code	B2
Filing date	Mar 9, 2016
Priority date	Mar 13, 2015
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

First claim

What is claimed is:

1. A microcontroller device comprising:
a plurality of external pins;
a first microcontroller comprising a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus,
a second microcontroller comprising a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus,
wherein first and second microcontroller are separate from each other and do not share any of their peripheral devices and communicate only via a dedicated interface,
wherein the dedicated interface comprises a bidirectional mailbox interface, a unidirectional master-slave interface and a unidirectional slave-master interface, and
wherein each unidirectional interface comprises a FIFO memory.

2. The microcontroller device according to claim 1 , wherein the dedicated interface further comprises a bidirectional mailbox interface.

3. The microcontroller device according to claim 2 , further comprising a common pad ownership multiplexer unit being controllable to assign control of input/output pins to either the first microcontroller or the second microcontroller.

4. The microcontroller device according to claim 1 , wherein the first microcontroller is a master and the second microcontroller is a slave.

5. The microcontroller device according to claim 4 , wherein a program memory of the second microcontroller comprises volatile memory which is writable by the first microcontroller.

6. The microcontroller device according to claim 5 , wherein the second microcontroller is clocked faster than the first microcontroller.

7. The microcontroller device according to claim 4 , wherein the second microcontroller comprises a power mode control unit configured to operate the second microcontroller in a low power mode, wherein the first microcontroller is coupled with the power mode control unit ( 520 ) and configured to control a power mode of the second microcontroller.

8. The microcontroller device according to claim 7 , wherein the power control mode unit is operable to disable the second microcontroller such that the second microcontroller does not consume any power.

9. The microcontroller device according to claim 7 , wherein each system bus has a data bus width of 16 bits.

10. The microcontroller device according to claim 1 , wherein each microcontroller further comprises a pin select unit programmable to select at least some of the plurality of external pins for the peripheral devices associated with the microcontroller.

11. The microcontroller device according to claim 1 , wherein each microcontroller further comprises a pad ownership multiplexer unit being controllable to assign control of predefined sets of input/output pins to selected peripherals of the first microcontroller or the second microcontroller, respectively.

12. The microcontroller device according to claim 11 , wherein each microcontroller can read any readable external pin but only pins assigned to the first or second microcontroller can be written by the respective microcontroller.

13. The microcontroller device according to claim 11 , wherein at least some of each of the peripherals of each microcontroller are assigned to predetermined external pins of a plurality of external pins.

14. A method of operating a microcontroller device comprising a plurality of external pins, a first microcontroller comprising a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller comprising a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller are separate from each other and do not share any of their peripheral devices, the method comprising:
communicating between the first and second microcontroller only via a dedicated interface, wherein the dedicated interface comprises a unidirectional master-slave interface and a unidirectional slave-master interface each comprising FIFO memory.

15. The method according to claim 14 , wherein the dedicated interface further comprises a bidirectional mailbox interface.

16. The method according to claim 15 , further comprising the step of assigning control of input/output pins to either the first microcontroller or the second microcontroller through a common pad ownership multiplexer unit.

17. The method according to claim 14 , wherein the first microcontroller is a master and the second microcontroller is a slave.

18. The method according to claim 17 , wherein a program memory of the second microcontroller comprises volatile memory and wherein the method comprises the step of writing to the program memory of the second microcontroller by the first microcontroller.

19. The method according to claim 18 , further comprising clocking the second microcontroller faster than the first microcontroller.

20. The method according to claim 17 , wherein the second microcontroller comprises a power mode control unit coupled with the first microcontroller and configured to control a power mode, including a low power mode, of the second microcontroller, the method further comprising the step of controlling by the first microcontroller a power mode of the second microcontroller through said power mode control unit.

21. The method according to claim 20 , comprising the step of disabling by the power control mode unit the second microcontroller such that the second microcontroller does not consume any power.

22. The method according to claim 14 , further comprising the step of controlling a pin ownership with respect to each microcontroller wherein predefined sets of input/output pins are assigned to selected peripherals of the first microcontroller or the second microcontroller, respectively.

23. The method according to claim 22 , wherein each microcontroller can read any readable external pin but only pins assigned to the first or second microcontroller can be written by the respective microcontroller.

24. The method according to claim 23 , further comprising the steps of
reading one of a plurality of external pins by the first microcontroller,
reading the one of a plurality of external pins by the second microcontroller,
comparing the value read from the one of the plurality of external pins by means of the dedicated interface.

25. The method according to claim 14 , further comprising the step of assigning control of input/output pins to either the first microcontroller or the second microcontroller by a common pad ownership multiplexer unit.

Assignees

• Microchip Tech Inc

Inventors

• Kris Bryan
• Wojewoda Igor
• Dumais Alex
• Catherwood Mike
• Fall Brian
• Tollefson Jason
• Wilke Calum
• Mickey Dave
• Spohrer Thomas
• Pepping Jim
• Sheard Vincent

Classifications

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic

• G06F13/1673 Primary

  using buffers · CPC title

• G06F1/22

  Means for limiting or controlling the pin/gate ratio · CPC title