Low-pin microcontroller device with multiple independent microcontrollers

Patent metadata

Field	Value
Publication number	US-10002102-B2
Application number	US-201615064964-A
Country	US
Kind code	B2
Filing date	Mar 9, 2016
Priority date	Mar 13, 2015
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.

First claim

What is claimed is:

1. A microcontroller device comprising:
a plurality of external pins comprising a plurality of input/output pins;
a first microcontroller comprising a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus,
a second microcontroller comprising a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and
a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller;
wherein each microcontroller comprises a peripheral pin select unit configured to assign a selected external pin which has been assigned by the pad ownership multiplexers to a respective microcontroller to a peripheral of that microcontroller;
wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.

2. The microcontroller device according to claim 1 , further comprising configuration registers that determine an assignment of the external pins, wherein the configuration registers are programmed during programming of the microcontroller device.

3. The microcontroller device according to claim 1 , further comprising special function registers that determine an assignment of the external pins.

4. The microcontroller device according to claim 3 , wherein the special function registers are programmable only by the first microcontroller.

5. The microcontroller device according to claim 1 , wherein the first microcontroller is a master and the second microcontroller is a slave, wherein a program memory of the second microcontroller comprises volatile memory which is writable by the first microcontroller.

6. The microcontroller device according to claim 1 , wherein each microcontroller has a data bus width of 16 bits.

7. The microcontroller device according to claim 1 , wherein first and second microcontroller communicate only via a dedicated interface.

8. The microcontroller device according to claim 7 , wherein the dedicated interface comprises a bidirectional mailbox interface, a unidirectional master-slave interface and a unidirectional slave-master interface.

9. The microcontroller device according to claim 8 , wherein each unidirectional interface comprises a FIFO memory.

10. The microcontroller device according to claim 1 , wherein each microcontroller can read any readable external pin but only pins assigned to the first or second microcontroller can be written by the respective microcontroller.

11. The microcontroller device according to claim 1 , wherein at least some of each of the peripherals of each microcontroller are assigned to predetermined external pins of said plurality of external input/output pins.

12. A microcontroller device comprising:
a plurality of external pins;
a first microcontroller comprising a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and
a second microcontroller comprising a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus,
wherein each microcontroller comprises a peripheral pin select unit configured to assign a selected external pin which has been assigned by the pad ownership multiplexers to a respective microcontroller to a peripheral of that microcontroller;
wherein a first subset of the plurality of external pins can only be assigned to the first microcontroller and a second subset of the plurality of external pins can only be assigned to the second microcontroller.

13. The microcontroller according to claim 12 , further comprising a first and second pad ownership multiplexer unit being controllable to assign control of the input/output pins to the first microcontroller or the second microcontroller, respectively.

14. The microcontroller device according to claim 13 , further comprising configuration registers that determine an assignment of the external pins, wherein the configuration registers are programmed during programming of the microcontroller device.

15. The microcontroller device according to claim 13 , further comprising special function registers that determine an assignment of the external pins.

16. The microcontroller device according to claim 15 , wherein the special function registers are programmable only by the first microcontroller.

17. The microcontroller device according to claim 13 , wherein each microcontroller can read any readable external pin but only pins assigned to the first or second microcontroller can be written by the respective microcontroller.

18. The microcontroller device according to claim 13 , wherein at least some of each of the peripherals of each microcontroller are assigned to predetermined external pins of said plurality of external input/output pins.

19. The microcontroller device according to claim 12 , wherein the first microcontroller is a master and the second microcontroller is a slave, wherein a program memory of the second microcontroller comprises volatile memory which is writable by the first microcontroller.

20. The microcontroller device according to claim 12 , wherein each microcontroller has a data bus width of 16 bits.

21. The microcontroller device according to claim 12 , wherein first and second microcontroller communicate only via a dedicated interface.

22. The microcontroller device according to claim 21 , wherein the dedicated interface comprises a bidirectional mailbox interface, a unidirectional master-slave interface and a unidirectional slave-master interface.

23. The microcontroller device according to claim 22 , wherein each unidirectional interface comprises a FIFO memory.

Assignees

• Microchip Tech Inc

Inventors

• Kris Bryan
• Wojewoda Igor
• Dumais Alex
• Catherwood Mike
• Fall Brian
• Tollefson Jason
• Wilke Calum
• Mickey Dave
• Spohrer Thomas

Classifications

• Y02D10/13

  Cross-Sectional Technologies · mapped topic

• G06F13/1673 Primary

  using buffers · CPC title

• G06F13/364 Primary

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic