In cell touch panel with uniformly-distributed grooves and display device

Patent metadata

Field	Value
Publication number	US-10001870-B2
Application number	US-201514892678-A
Country	US
Kind code	B2
Filing date	Apr 13, 2015
Priority date	Jan 9, 2015
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

An In Cell touch panel and a display device are disclosed. The insulating layer comprises at least one groove at overlapping regions between each self capacitance electrode and the wires. Via holes penetrating the insulating layer are arranged in the insulating layer at overlapping regions between corresponding wires and self capacitance electrodes. Recesses not penetrating the insulating layer are arranged in the insulating layer at overlapping regions between wires and self capacitance electrodes apart from the corresponding wires and self capacitance electrodes. Thus, only the corresponding wires and self capacitance electrodes are electrically connected with each other, and the insulating layer is further provided with grooves at overlapping regions between wires and self capacitance electrodes which are not electrically connected. Grooves are distributed uniformly in the insulating layer and the problem of non-uniform displayed picture due to non-uniform distribution of via holes in the insulating layer is solved.

First claim

The invention claimed is:

1. An in cell touch panel, comprising:
an upper substrate and a lower substrate which are arranged oppositely,
a plurality of independent self capacitance electrodes which are arranged on a surface of the upper substrate facing the lower substrate or a surface of the lower substrate facing the upper substrate;
wires which are arranged in a different layer from that of the self capacitance electrodes and are electrically connected with each self capacitance electrode;
and an insulating layer between the self capacitance electrodes and the wires;
wherein the insulating layer comprises at least one groove at overlapping regions between the self capacitance electrodes and the wires;
wherein the grooves at the overlapping regions between the self capacitance electrodes and the corresponding wires are via holes penetrating the insulating layer, the self capacitance electrodes are electrically connected with the corresponding wires through respective via holes; and
wherein except for grooves for electrically connecting the corresponding wires with the self capacitance electrodes, the remaining grooves are recesses not penetrating the insulating layer;
wherein the insulating layer between each self capacitance electrode and the wires which are electrically connected consists of a first passivation layer and a second passivation layer which are successively arranged above the wires; and
wherein the insulating layer between the self capacitance electrodes and the wires which are not electrically connected consists of the first passivation layer, a pixel electrode layer, and the second passivation layer which are successively arranged above the wires, and wherein the recesses in the insulating layer only penetrate the second passivation layer so that the self capacitance electrode is electrically connected with the pixel electrode layer.

2. The in cell touch panel of claim 1 , wherein each groove has a same shape and size.

3. The in cell touch panel of claim 1 , wherein each wire has a same extending direction.

4. The in cell touch panel of claim 3 , wherein each wire has a same length.

5. The in cell touch panel of claim 4 , wherein as for each self capacitance electrode, grooves in the overlapping regions between the self capacitance electrodes and the wires which are not electrically connected are distributed in the same manner as grooves in the overlapping regions between the self capacitance electrodes and the wires which are electrically connected.

6. The in cell touch panel of claim 5 , wherein as for each wire, the distance between any two neighboring grooves which overlap the wires is constant.

7. The in cell touch panel of claim 1 , wherein the self capacitance electrodes form a common electrode layer on the surface of the lower substrate facing the upper substrate.

8. The in cell touch panel of claim 7 , wherein the in cell touch panel further comprises a touch detecting chip, wherein the touch detecting chip is configured to apply a common electrode signal to each self capacitance electrode during a display period, and determine a touch position by detecting variation in capacitance value of each self capacitance electrode during a touch period.

9. The in cell touch panel of claim 8 , further comprising a data line below the self capacitance electrode.

10. The in cell touch panel of claim 9 , wherein the wires and the data lines are arranged in a same layer and formed by a same material.

11. The in cell touch panel of claim 9 , further comprising: a black matrix layer which is arranged on the surface of the lower substrate facing the upper substrate or the surface of the upper substrate facing the lower substrate.

12. The in cell touch panel of claim 11 , wherein an orthographic projection of a pattern of each wire onto the lower substrate falls within a region where a pattern of the black matrix layer is located.

13. The in cell touch panel of claim 1 , wherein the via holes penetrate the first passivation layer and the second passivation layer.

14. A display device, comprising an in cell touch panel, wherein the in cell touch panel comprises:
an upper substrate and a lower substrate which are arranged oppositely;
a plurality of independent self capacitance electrodes which are arranged on a surface of the upper substrate facing the lower substrate or a surface of the lower substrate facing the upper substrate;
wires which are arranged in a different layer from that of the self capacitance electrodes and are electrically connected with the self capacitance electrodes; and
an insulating layer between the self capacitance electrodes and the wires;
wherein the insulating layer comprises at least one groove at overlapping regions between the self capacitance electrodes and the wires;
wherein the grooves at the overlapping regions between the self capacitance electrodes and the corresponding wires are via holes penetrating the insulating layer, the self capacitance electrodes are electrically connected with the corresponding wires through respective via holes; and
wherein except for grooves for electrically connecting the corresponding wires with the self capacitance electrodes, the remaining grooves are recesses not penetrating the insulating layer;
wherein the insulating layer between each self capacitance electrode and the wires which are electrically connected consists of a first passivation layer and a second passivation layer which are successively arranged above the wires; and
wherein the insulating layer between the self capacitance electrodes and the wires which are not electrically connected consists of the first passivation layer, a pixel electrode layer, and the second passivation layer which are successively arranged above the wires, and wherein the recesses in the insulating layer only penetrate the second passivation layer so that the self capacitance electrode is electrically connected with the pixel electrode layer.

15. The display device of claim 14 , wherein as for each self capacitance electrode, grooves in the overlapping regions between the self capacitance electrodes and the wires which are not electrically connected are distributed in the same manner as grooves in the overlapping regions between the self capacitance electrodes and the wires which are electrically connected.

16. The display device of claim 14 , wherein the in cell touch panel further comprises a touch detecting chip, wherein the touch detecting chip is configured to apply a common electrode signal to the self capacitance electrodes during a display period, and determine a touch position by detecting variation in capacitance value of the self capacitance electrodes during a touch period.

17. The display device of claim 14 , wherein the in cell touch panel further comprises: a black matrix layer which is arranged on the surface of the lower substrate facing the upper substrate or the surface of the upper substrate facing the lower substrate.

18. The display device of claim 17 , wherein an orthographic projection of a pattern of each wire onto the lower substrate falls within a region where a pattern of the black matrix layer is located.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optolectronics Tech Co Ltd

Inventors

• Li Yanchen

Classifications

• G02F1/133514 Primary

  Colour filters · CPC title

• G06F3/0412

  Digitisers structurally integrated in a display · CPC title

• G06F2203/04111

  Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate · CPC title

• G06F3/044 Primary

  by capacitive means · CPC title

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title