Input-output device management using dynamic clock frequency

Patent metadata

Field	Value
Publication number	US-10001830-B2
Application number	US-201514728918-A
Country	US
Kind code	B2
Filing date	Jun 2, 2015
Priority date	Jun 16, 2014
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

In an example, a method includes determining, at a host device, a power state of a digital input/output device, and transmitting a clock signal having a first frequency from the host device to the input/output device responsive to a determination that the input/output device is in a lower power state. The method also includes determining, at the host device, that the input/output device has transitioned into a higher power state, and transmitting a clock signal having a second frequency from the host device to the input/output device responsive to a determination that the input/output device has transitioned into the higher power state. The first frequency is lower than the second frequency.

First claim

What is claimed is:

1. A method comprising:
determining, at a host device, a power state of a digital input/output device embedded in the host device;
transmitting a clock signal having a first frequency from the host device to the input/output device responsive to a determination that the input/output device is in a lower power state;
determining, at the host device, that the input/output device has transitioned into a higher power state based on a message received from the input/output device, the message comprising a confirmation of a command to retrieve data from the input/output device or write data to the input/output device; and
transmitting a clock signal having a second frequency from the host device to the input/output device responsive to a determination that the input/output device has transitioned into the higher power state,
wherein the first frequency is lower than the second frequency.

2. The method of claim 1 , wherein the command comprises a CMD52 command or a CMD53 command in accordance with a secure digital input/output (SDIO) standard.

3. The method of claim 1 , wherein the message comprises an indication that the input/output device has successfully transitioned into the higher power state.

4. The method of claim 1 , wherein the lower power state corresponds to a sleep state of the input/output device, and wherein the higher power state corresponds to an active state of the SDIO device.

5. The method of claim 1 , wherein the lower power state corresponds to a data transmission conducted by the input/output device according to a first communication standard, and wherein the higher power state corresponds to a data transmission conducted by the input/output device according to a second communication standard.

6. The method of claim 5 , wherein the first communication standard is Bluetooth and the second communication standard is Wi-Fi, and
wherein the host device operates according to a first dynamic power range while transmitting data according to the first communication standard, and the host device operates according to a second dynamic power range while transmitting data according to the second communication standard, wherein the first dynamic power range is greater than the second dynamic power range.

7. The method of claim 1 , further comprising:
determining, at the host device, that the input/output device is transitioning into the lower power state; and
transmitting a clock signal having the first frequency from the host device to the input/output device responsive to a determination that the input/output device is transitioning into the lower power state.

8. The method of claim 7 , wherein determining that the input/output device is transitioning into the lower power state comprises:
transmitting, from the host device to the input/output device, a second command to enter the lower power state;
receiving, at the host device from the input/output device, a second message responsive to the second command; and
determining, at the host device, that the input/output device is transitioning into the lower power state based on the second message.

9. The method of claim 1 , further comprising:
transmitting, from the host device to the input/output device, a request to enumerate the first frequency and the second frequency; and
receiving, at the host device from the input/output device, an indication of the first frequency and an indication of the second frequency.

10. The method of claim 1 , wherein the input/output device is a secure digital input/output (SDIO) device.

11. A digital input/output device comprising:
an interface module configured to communicatively couple with a host device;
a power module configured to couple with a power supply;
a network module; and
a controller coupled with the interface module and the power module, the controller being configured to:
transmit, to the host device via the interface module, a first message indicating that the input/output device is in a lower power state;
responsive to transmitting the first message, receive, from the host device via the interface module, a first clock signal having a first frequency;
transmit, to the host device via the interface module, a second message indicating that the input/output device has transitioned into a higher power state;
responsive to transmitting the second message, receive, from the host device via the interface module, a second clock signal having a second frequency;
cause the power module to draw power from the power supply according to a first power range while the interface module is receiving the first clock signal;
cause the power module to draw power from the power supply according to a second power range while the interface module is receiving the second clock signal;
direct the network module to transmit data according to a first communication standard while the input/output device is in the higher power state; and
direct the network module transmit data according to a second communication standard while the input/output device is in the lower power state,

wherein the first frequency is lower than the second frequency, and wherein the first power range is less than the second power range, and
wherein the digital input/output device is configured to be embedded in the host device.

12. The digital input/output device of claim 11 , wherein the second message comprises a confirmation of a command to retrieve data from the input/output device or write data to the input/output device.

13. The digital input/output device of claim 12 , wherein the command comprises a CMD52 command or a CMD53 command in accordance with a secure digital input/output (SDIO) standard.

14. The digital input/output device of claim 11 , wherein the second message comprises an indication that the input/output device has successfully transitioned into the higher power state.

15. The digital input/output device of claim 11 , wherein the first communication standard is Wi-Fi and the second communication standard is Bluetooth.

16. The digital input/output device of claim 11 , wherein the controller is further configured to:
transmit, to the host device via the interface module, a third message that the input/output device is transitioning into the lower power state; and
responsive to transmitting the third message, receive, from the host device via the interface module, the first clock signal having the first frequency.

17. The digital input/output device of claim 11 , wherein the power module is configured to:
apply a first core voltage to a processing circuit of the controller while the interface module is receiving the first clock signal; and
apply a second core voltage to the processing circuit of the controller while the interface module is receiving the second clock signal,
wherein the first core voltage is less than the second core voltage.

18. The digital input/output device of claim 11 , wherein the controller is configured to generate an internal clock signal while the input/output device is in the higher power state, and not generate the internal clock signal while the input/output device is in the lower power state.

19. The digital input/output device of claim 11 , wherein the digital input/output device is a secure digital input/output (SDIO) device.

20. A system comprising:
a host device; and
a digital input/output device embedded in the host device;
wherein the input/output device is configured to:
transmit, to the host device, a first message indicating that the input/outpu

Assignees

• Marvell World Trade Ltd

Inventors

• Chau Benson
• Huang Frank
• Luo Xiaohua
• Shanmugasundaram Venkatachalam

Classifications

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/325 Primary

  Power saving in peripheral device · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title