Charge packet signal processing using pinned photodiode devices

Patent metadata

Field	Value
Publication number	US-10001406-B2
Application number	US-201615175958-A
Country	US
Kind code	B2
Filing date	Jun 7, 2016
Priority date	Jun 7, 2016
Publication date	Jun 19, 2018
Grant date	Jun 19, 2018

Abstract

An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.

First claim

What is claimed is:

1. A method of operating an image sensor that includes a pixel with an output line, the method comprising:
with first charge transfer circuitry that includes at least a first pinned photodiode, transferring a first amount of charge to a first capacitive node that is coupled to a first input of a comparator;
with a sampling transistor, sampling a pixel signal onto a second capacitive node that is coupled to a second input of the comparator; and
with second charge transfer circuitry that includes at least a second pinned photodiode, transferring a second amount of charge to the second capacitive node.

2. The method defined in claim 1 , further comprising:
comparing voltages at the first and second inputs of the comparator; and
transferring a third amount of charge to the first capacitive node with the first charge transfer circuitry in response to determining that the voltage at the first input of the comparator is greater than the voltage at the second input of the comparator, wherein the second charge transfer circuitry is used to transfer the second amount of charge in response to determining that the voltage at the first input of the comparator is less than the voltage at the second input of the comparator.

3. The method defined in claim 2 , wherein transferring the third amount of charge comprises:
transferring half of the first amount of charge to the first capacitive node.

4. The method defined in claim 1 , wherein transferring the first amount of charge comprises:
performing a first number of charge transfers with the first charge transfer circuit, wherein each of the first number of charge transfer transfers an amount of charge based on a full-well capacity of the first pinned photodiode in the first charge transfer circuit.

5. The method defined in claim 4 , wherein transferring the second amount of charge comprises:
performing a second number of charge transfers with the first charge transfer circuit, wherein the second number is less than the first number.

6. The method defined in claim 4 , further comprising:
with at least a first plurality of charge transfer circuits, performing the first number of charge transfers with each of the charge transfer circuits in the first plurality of charge transfer circuits while the first charge transfer circuit is transferring charge.

7. The method defined in claim 1 , wherein transferring the second amount of charge comprises:
transferring half of the first amount of charge to the second capacitive node.

8. The method defined in claim 1 , wherein sampling the pixel signal comprises:
receiving a first voltage level from the pixel output line at a level shifting circuit; and
with the level shifting circuit, shifting the first voltage level to a second voltage level that is greater than the first voltage; and
providing the shifted voltage to the sampling transistor.

9. The method defined in claim 1 , wherein the first charge transfer circuitry is coupled to a first fill voltage supply, and wherein the second charge transfer circuitry is coupled to a second fill voltage supply, the method further comprising:
adjusting the first and second fill voltage supply values while using the first and second charge transfer circuitry for charge transfer operations.

10. The method of claim 1 , wherein the first charge transfer circuitry comprises a first plurality of charge transfer stages, the method further comprising:
performing a plurality of charge transfer operations, wherein each of the plurality of charge transfer operations use different subsets of the first plurality of charge transfer stages.

11. The method of claim 1 , the method further comprising:
performing a plurality of charge transfer operations, wherein each of the plurality of charge transfer operations transfers a different amount of charge to the first capacitive node.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Panicacci Roger

Classifications

• G01J1/4228 Primary

  arrangements with two or more detectors, e.g. for sensitivity compensation · CPC title

• G01J2001/446

  Photodiode · CPC title

• G01J1/44

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title

• H04N25/78 Primary

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title