Systems and methods for adaptive hybrid hardware pre-fetch
US-12282429-B2 · Apr 22, 2025 · US
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Zadeh Ehsan Khish Ardestani patents
Zadeh Ehsan Khish Ardestani is listed as an inventor on 27 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Zadeh Ehsan Khish Ardestani |
| Total patents | 27 |
| First publication | Nov 19, 2020 |
| Latest publication | Apr 22, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Systems and methods for reducing power consumption of convolution operations of artificial neural networks
US-11599181-B1 · Mar 7, 2023 · US
Grouped convolution using point-to-point connected channel convolution engines
US-11580192-B2 · Feb 14, 2023 · US
Systems and methods for adaptive hybrid hardware pre-fetch
US-2023022190-A1 · Jan 26, 2023 · US
Mapping convolution to a channel convolution engine
US-11537865-B2 · Dec 27, 2022 · US
Support for different matrix multiplications by selecting adder tree intermediate results
US-11520854-B2 · Dec 6, 2022 · US
Mapping convolution to a partition channel convolution engine
US-11520853-B2 · Dec 6, 2022 · US
Mapping convolution to a matrix processor unit
US-11481471-B2 · Oct 25, 2022 · US
Using a low-bit-width dot product engine to sum high-bit-width numbers
US-11455143-B2 · Sep 27, 2022 · US
Pipelined pointwise convolution using per-channel convolution operations
US-11443013-B2 · Sep 13, 2022 · US
Recent patents
Latest publications not already listed above.
High throughput matrix processor with support for concurrently processing multiple matrices
US-11409838-B2 · Aug 9, 2022 · US
Device and method for flexibly summing matrix values
US-11379557-B2 · Jul 5, 2022 · US
Floating point multiply hardware using decomposed component numbers
US-2022107782-A1 · Apr 7, 2022 · US
Floating point multiply hardware using decomposed component numbers
US-11188303-B2 · Nov 30, 2021 · US
Using a low-bit-width dot product engine to sum high-bit-width numbers
US-2021349690-A1 · Nov 11, 2021 · US
Device and method for flexibly summing matrix values
US-2021349965-A1 · Nov 11, 2021 · US
Mapping convolution to connected processing elements using distributed pipelined separable convolution operations
US-2021334072-A1 · Oct 28, 2021 · US
Grouped convolution using point-to-point connected channel convolution engines
US-2021319076-A1 · Oct 14, 2021 · US
Pipelined pointwise convolution using per-channel convolution operations
US-2021294875-A1 · Sep 23, 2021 · US
Mapping convolution to a partition channel convolution engine
US-2021271451-A1 · Sep 2, 2021 · US
Mapping convolution to a channel convolution engine
US-2021256363-A1 · Aug 19, 2021 · US
Support for different matrix multiplications by selecting adder tree intermediate results
US-2021125044-A1 · Apr 29, 2021 · US
High throughput matrix processor with support for concurrently processing multiple matrices
US-2021124794-A1 · Apr 29, 2021 · US
Floating point multiply hardware using decomposed component numbers
US-2021103429-A1 · Apr 8, 2021 · US
Mapping convolution to a matrix processor unit
US-2021049229-A1 · Feb 18, 2021 · US
Memory organization for matrix processing
US-10872038-B1 · Dec 22, 2020 · US
High throughput neural network operations using inter-layer memory layout transformation
US-2020364047-A1 · Nov 19, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Facebook Inc | 15 |
| Meta Platforms Inc | 10 |
| Huawei Tech Co Ltd | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F17/16 | 25 |
| G06N3/063 | 21 |
| G06N3/045 | 15 |
| G06N3/0464 | 14 |
| G06F17/153 | 14 |