Masked multi-lane instruction memory fault handling using fast and slow execution paths
US-11847463-B2 · Dec 19, 2023 · US
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Weidner Robert patents
Weidner Robert is listed as an inventor on 2 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Weidner Robert |
| Total patents | 2 |
| First publication | Apr 1, 2021 |
| Latest publication | Dec 19, 2023 |
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Advanced Micro Devices Inc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30038 | 2 |
| G06F9/3887 | 2 |
| G06F9/30036 | 2 |
| G06F9/3861 | 2 |
| G06F9/30145 | 2 |