Methods and apparatus for automatic communication optimizations in a compiler based on a polyhedral representation
US-11989536-B1 · May 21, 2024 · US
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Vasilache Nicolas T patents
Vasilache Nicolas T is listed as an inventor on 17 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Vasilache Nicolas T |
| Total patents | 17 |
| First publication | Jan 6, 2015 |
| Latest publication | May 21, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
System and method for configuration of an ensemble solver
US-11797894-B1 · Oct 24, 2023 · US
System and method for generation of event driven, tuple-space based programs
US-11789769-B2 · Oct 17, 2023 · US
Efficient and scalable storage of sparse tensors
US-11573945-B1 · Feb 7, 2023 · US
System and method for generation of event driven, tuple-space based programs
US-2022004425-A9 · Jan 6, 2022 · US
Methods and apparatus for automatic communication optimizations in a compiler based on a polyhedral representation
US-11200035-B1 · Dec 14, 2021 · US
System and method for generation of event driven, tuple-space based programs
US-2021255891-A1 · Aug 19, 2021 · US
Efficient and scalable computations with sparse tensors
US-10936569-B1 · Mar 2, 2021 · US
System and method for configuration of an ensemble solver
US-10839297-B1 · Nov 17, 2020 · US
System and method for generation of event driven, tuple-space based programs
US-10564949-B2 · Feb 18, 2020 · US
Recent patents
Latest publications not already listed above.
Methods and apparatus for automatic communication optimizations in a compiler based on a polyhedral representation
US-9830133-B1 · Nov 28, 2017 · US
System and method for configuration of an ensemble solver
US-9684865-B1 · Jun 20, 2017 · US
Methods and apparatus for joint scheduling and layout optimization to enable multi-level vectorization
US-9489180-B1 · Nov 8, 2016 · US
Systems and methods for parallelizing and optimizing sparse tensor computations
US-9471377-B2 · Oct 18, 2016 · US
Systems and methods for parallelizing and optimizing sparse tensor computations
US-2015169369-A1 · Jun 18, 2015 · US
System and method for generation of event driven, tuple-space based programs
US-2015089485-A1 · Mar 26, 2015 · US
System, methods and apparatus for program optimization for multi-threaded processor architectures
US-8930926-B2 · Jan 6, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Reservoir Labs Inc | 13 |
| Qualcomm Inc | 4 |
| Qualcomm Technologies Inc | 3 |
| Significs And Elements Llc | 2 |
| Bastoul Cedric | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F2209/483 | 4 |
| G06F9/4881 | 4 |
| G06F8/453 | 4 |
| G06N5/01 | 3 |
| G06N5/02 | 3 |