Cache load balancing in a virtual input/output server
US-10740157-B2 · Aug 11, 2020 · US
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Shrigiri Girish patents
Shrigiri Girish is listed as an inventor on 4 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Shrigiri Girish |
| Total patents | 4 |
| First publication | Feb 1, 2018 |
| Latest publication | Aug 11, 2020 |
Notable patents
Publications ranked by popularity score, then publication date.
Cache load balancing in a virtual input/output server
US-2019370082-A1 · Dec 5, 2019 · US
Efficiency in active memory sharing
US-10228859-B2 · Mar 12, 2019 · US
Efficiency in active memory sharing
US-2018032250-A1 · Feb 1, 2018 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 4 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/5077 | 4 |
| G06F9/45533 | 4 |
| G06F9/5016 | 4 |
| G06F2009/45583 | 3 |
| G06F9/45558 | 3 |