Apparatus and method for managing unsupported instruction set architecture (ISA) features in a virtualized environment
US-12223318-B2 · Feb 11, 2025 · US
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Sheffield David patents
Sheffield David is listed as an inventor on 15 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Sheffield David |
| Total patents | 15 |
| First publication | Apr 2, 2020 |
| Latest publication | Feb 11, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Apparatus and method for booting an application processor
US-2024320341-A1 · Sep 26, 2024 · US
Apparatus and Method for an Efficient System Management Mode
US-2024320002-A1 · Sep 26, 2024 · US
Apparatus and method for switching between page table types
US-2024143513-A1 · May 2, 2024 · US
Apparatus and method for managing deprecated instruction set architecture (isa) features
US-2024143361-A1 · May 2, 2024 · US
Apparatus and method for managing unsupported instruction set architecture (isa) features in a virtualized environment
US-2022308867-A1 · Sep 29, 2022 · US
Apparatus and method for adaptable and efficient lane-wise tensor processing
US-11379229-B2 · Jul 5, 2022 · US
Apparatus and method for gang invariant operation optimizations using dynamic evaluation
US-11093250-B2 · Aug 17, 2021 · US
Apparatus and method for a high throughput parallel co-processor and interconnect with low offload latency
US-10915328-B2 · Feb 9, 2021 · US
Apparatus and method for adaptable and efficient lane-wise tensor processing
US-2020364045-A1 · Nov 19, 2020 · US
Recent patents
Latest publications not already listed above.
Architecture and method for data parallel single program multiple data (SPMD) execution
US-10831505-B2 · Nov 10, 2020 · US
Apparatus and method for adaptable and efficient lane-wise tensor processing
US-10776110-B2 · Sep 15, 2020 · US
Apparatus and method for a high throughput parallel co-processor and interconnect with low offload latency
US-2020192676-A1 · Jun 18, 2020 · US
Apparatus and method for adaptable and efficient lane-wise tensor processing
US-2020104126-A1 · Apr 2, 2020 · US
Architecture and method for data parallel single program multiple data (spmd) execution
US-2020104139-A1 · Apr 2, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 15 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/3888 | 9 |
| G06F9/3851 | 9 |
| G06F9/30145 | 7 |
| G06F9/30038 | 5 |
| G06F9/30036 | 5 |