Device, method and system to throttle circuit operations based on a requested memory refresh rate
US-2025218485-A1 · Jul 3, 2025 · US
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Offen Zeev patents
Offen Zeev is listed as an inventor on 26 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Offen Zeev |
| Total patents | 26 |
| First publication | Feb 10, 2015 |
| Latest publication | Jul 3, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Controlling operating voltage of a processor
US-2022113779-A1 · Apr 14, 2022 · US
Controlling operating voltage of a processor
US-11175712-B2 · Nov 16, 2021 · US
Controlling Operating Voltage Of A Processor
US-2019354155-A1 · Nov 21, 2019 · US
Interface for communication between circuit blocks of an integrated circuit, and associated apparatuses, systems, and methods
US-10401928-B2 · Sep 3, 2019 · US
Controlling operating voltage of a processor
US-10394300-B2 · Aug 27, 2019 · US
Technique to share information among different cache coherency domains
US-10204051-B2 · Feb 12, 2019 · US
Controlling Operating Voltage Of A Processor
US-2018314307-A1 · Nov 1, 2018 · US
Technique to share information among different cache coherency domains
US-10078590-B2 · Sep 18, 2018 · US
Controlling operating voltage of a processor
US-9996135-B2 · Jun 12, 2018 · US
Recent patents
Latest publications not already listed above.
Technique to share information among different cache coherency domains
US-9946650-B2 · Apr 17, 2018 · US
Context save and restore
US-9898298-B2 · Feb 20, 2018 · US
North complex/south complex interface
US-2017242708-A1 · Aug 24, 2017 · US
Technique to share information among different cache coherency domains
US-9665488-B2 · May 30, 2017 · US
Technique to share information among different cache coherency domains
US-2017109280-A1 · Apr 20, 2017 · US
Technique to share information among different cache coherency domains
US-2017109304-A1 · Apr 20, 2017 · US
Technique to share information among different cache coherency domains
US-2017109287-A1 · Apr 20, 2017 · US
Interface for communication between circuit blocks of an integrated circuit, and associated apparatuses, systems, and methods
US-9594413-B2 · Mar 14, 2017 · US
Controlling Operating Voltage Of A Processor
US-2016259389-A1 · Sep 8, 2016 · US
Independently controlling frequency of plurality of power domains in a processor system
US-9395784-B2 · Jul 19, 2016 · US
Controlling operating voltage of a processor
US-9367114-B2 · Jun 14, 2016 · US
Execution context swap between heterogeneous functional hardware units
US-9250901-B2 · Feb 2, 2016 · US
Method and apparatus for monitor and MWAIT in a distributed cache architecture
US-9239789-B2 · Jan 19, 2016 · US
Method and apparatus for monitor and mwait in a distributed cache architecture
US-2015286568-A1 · Oct 8, 2015 · US
Technique to share information among different cache coherency domains
US-9035962-B2 · May 19, 2015 · US
Split deep power down of I/O module
US-8954771-B2 · Feb 10, 2015 · US
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