Encoder neural networks with power constrained latent representations
US-2026073662-A1 · Mar 12, 2026 · US
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Mark William R patents
Mark William R is listed as an inventor on 28 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Mark William R |
| Total patents | 28 |
| First publication | Oct 27, 2016 |
| Latest publication | Mar 12, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Convolutional neural network on programmable two dimensional image processor
US-12020027-B2 · Jun 25, 2024 · US
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US-11196953-B2 · Dec 7, 2021 · US
Convolutional neural network on programmable two dimensional image processor
US-2021004633-A1 · Jan 7, 2021 · US
Convolutional neural network on programmable two dimensional image processor
US-10789505-B2 · Sep 29, 2020 · US
Macro I/O unit for image processor
US-10733956-B2 · Aug 4, 2020 · US
Architecture for high performance, power efficient, programmable image processing
US-10719905-B2 · Jul 21, 2020 · US
Macro I/O Unit for Image Processor
US-2020160809-A1 · May 21, 2020 · US
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US-2020154072-A1 · May 14, 2020 · US
Convolutional neural network on programmable two dimensional image processor
US-10546211-B2 · Jan 28, 2020 · US
Recent patents
Latest publications not already listed above.
Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
US-2020020069-A1 · Jan 16, 2020 · US
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US-10531030-B2 · Jan 7, 2020 · US
Architecture for high performance, power efficient, programmable image processing
US-2019378239-A1 · Dec 12, 2019 · US
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US-2019327437-A1 · Oct 24, 2019 · US
Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
US-10387988-B2 · Aug 20, 2019 · US
Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
US-10387989-B2 · Aug 20, 2019 · US
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US-10334194-B2 · Jun 25, 2019 · US
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US-2018234653-A1 · Aug 16, 2018 · US
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US-9986187-B2 · May 29, 2018 · US
Architecture for high performance, power efficient, programmable image processing
US-9965824-B2 · May 8, 2018 · US
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US-2018007303-A1 · Jan 4, 2018 · US
Block Operations For An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register
US-2018007302-A1 · Jan 4, 2018 · US
Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register
US-2018005346-A1 · Jan 4, 2018 · US
Convolutional Neural Network On Programmable Two Dimensional Image Processor
US-2018005074-A1 · Jan 4, 2018 · US
Convolutional neural network on programmable two dimensional image processor
US-2018005075-A1 · Jan 4, 2018 · US
Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
US-2017287103-A1 · Oct 5, 2017 · US
Compiler Techniques for Mapping Program Code to a High Performance, Power Efficient, Programmable Image Processing Hardware Platform
US-2017249716-A1 · Aug 31, 2017 · US
Architecture for high performance, power efficient, programmable image processing
US-2016314555-A1 · Oct 27, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Google Llc | 20 |
| Google Inc | 8 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06T1/20 | 27 |
| G06F9/3001 | 16 |
| G06T2200/28 | 13 |
| G06T1/60 | 12 |
| G06F15/8023 | 10 |