Cell architecture with forksheet and gate-all-around devices
US-2026096195-A1 · Apr 2, 2026 · US
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Luo Yanbin patents
Luo Yanbin is listed as an inventor on 33 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Luo Yanbin |
| Total patents | 33 |
| First publication | Mar 14, 2024 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Complementary gate cut plugs for strain optimization
US-2026090024-A1 · Mar 26, 2026 · US
Defect-free epitaxial source and drain structures for ribbon field effect transistors
US-2026090023-A1 · Mar 26, 2026 · US
Improved removal of sacrificial material for minimized channel extensions
US-2026090039-A1 · Mar 26, 2026 · US
Fin trim plug structures with metal for imparting channel stress
US-12588252-B2 · Mar 24, 2026 · US
Backside contact structure with enhanced ohmic contact
US-2026032960-A1 · Jan 29, 2026 · US
Integrated circuit structure with zero diffusion break and wrap-around contact
US-2026006837-A1 · Jan 1, 2026 · US
Backside etch processes for ultra uniformity of front-end structures
US-2026005067-A1 · Jan 1, 2026 · US
Integrated circuit structures having stress-inducing gate cut plugs
US-2026006860-A1 · Jan 1, 2026 · US
Transistor metallization endcap scaling for performance optimization
US-2026006833-A1 · Jan 1, 2026 · US
Recent patents
Latest publications not already listed above.
Self-aligned fork-last backbone for forksheet transistors
US-2026006842-A1 · Jan 1, 2026 · US
Silicon source and drain trench fill for wider contacts
US-2026006906-A1 · Jan 1, 2026 · US
Sacrificial ribbon for uniform workfunction and capacitance benefits
US-2026006846-A1 · Jan 1, 2026 · US
Integrated circuit structures having hybrid channel layout
US-2025393250-A1 · Dec 25, 2025 · US
Integrated circuit structure with deep via bar width tuning
US-2025323127-A1 · Oct 16, 2025 · US
Zero diffusion break for improving transistor density
US-2025311273-A1 · Oct 2, 2025 · US
Selective channel width scaling using implants
US-2025311283-A1 · Oct 2, 2025 · US
Backside gate cut formation
US-2025311363-A1 · Oct 2, 2025 · US
Deep via backside (dvb) partial recess for capacitance reduction in complementary fet (cfet) transistors
US-2025311427-A1 · Oct 2, 2025 · US
Integrated circuit device with backside isolaton region
US-2025212470-A1 · Jun 26, 2025 · US
Integrated circuit structures with different nanoribbon thicknesses
US-2025169130-A1 · May 22, 2025 · US
Integrated circuit devices with backside semiconductor structures
US-2025140649-A1 · May 1, 2025 · US
Nbti reduction and reliability improvement for selective layouts
US-2025113586-A1 · Apr 3, 2025 · US
Multiple voltage threshold integrated circuit structure with local layout effect tuning
US-2025113595-A1 · Apr 3, 2025 · US
Integrated circuit structure with deep via bar width tuning
US-2025112120-A1 · Apr 3, 2025 · US
Integrated circuit structures having reduced local layout effects
US-2025107175-A1 · Mar 27, 2025 · US
Performance optimization of transistors sharing channel structures of varying width
US-2025006734-A1 · Jan 2, 2025 · US
Integrated circuit device with reduced n-p boundary effect
US-2024321887-A1 · Sep 26, 2024 · US
Integrated circuit device with performance-enhancing layout
US-2024321859-A1 · Sep 26, 2024 · US
Ultra-low voltage transistor cell design using gate cut layout
US-2024113118-A1 · Apr 4, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 33 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 27 |
| H10D30/6735 | 25 |
| H10D62/121 | 23 |
| H10D30/6757 | 22 |
| H10D30/43 | 21 |