Offset vertical interconnect and compression post for 3D-integrated electrical device
US-12593525-B2 · Mar 31, 2026 · US
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Farrell Stuart patents
Farrell Stuart is listed as an inventor on 5 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Farrell Stuart |
| Total patents | 5 |
| First publication | Aug 6, 2015 |
| Latest publication | Mar 31, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Low-stress dielectric layer, planarization method, and low-temperature processing for 3d-integrated electrical device
US-2022416095-A1 · Dec 29, 2022 · US
Offset vertical interconnect and compression post for 3d-integrated electrical device
US-2022293661-A1 · Sep 15, 2022 · US
Controlling the stoichiometry and doping of semiconductor materials
US-9419170-B2 · Aug 16, 2016 · US
Controlling the stoichiometry and doping of semiconductor materials
US-2015221810-A1 · Aug 6, 2015 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Raytheon Co | 3 |
| Alliance Sustainable Energy | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10F30/10 | 3 |
| H10F39/811 | 3 |
| H10F77/1233 | 2 |
| H10F71/125 | 2 |
| H01L31/1828 | 2 |